Abstract: A circuit arrangement for producing high current pulses includes a first constant current source for generating current pulses connected to a charged capacitor arranged so that the effective operating voltage of the constant current source is increased and a voltage limiting circuit that serves to limit the voltage potential impressed across the first constant current source. During the interval between current pulses, the voltage limiting circuit isolates the capacitor from the load and a series path is established which includes a second constant current source for charging the capacitor at a controlled rate.

Abstract: A conference arrangement for use in pulse code modulated telecommunication systems including first and second control memories and a comparison logic circuit. Two words corresponding to two channels are read from information memory during each time slot and after proper comparison, the largest sample is transmitted to a third channel.

Abstract: Support members are located near the corners of a pair of printed circuit cards for holding them together in a fixed, spaced-apart, adjacent and parallel relationship. Each card has a group of holes formed in the same pattern in each of the four corners thereof, at least one hole of each group extending all the way through the card. Each support member comprises a pair of plates that are joined together at a 90.degree. angle along one edges thereof. Load-bearing pegs project from parallel, non-joined together edges of one plate. Flexible posts project from parallel, non-joined together edges of the other plate. An arm extends from each post proximate the end thereof that is spaced from the other plate and in a direction substantially parallel to said parallel edges of the other plate.

Abstract: In a system employing half-span preemphasis of transmitted signals on a cable pair telephone line, equalization is accomplished in a circuit arrangement including first and second complementary constant-resistance networks having the input impedances thereof in the emitter and collector circuits, respectively, of a common emitter amplifier. These impedances control the feedback and gain of the amplifier such that their effects are additive in a particular manner in the collector-output circuit thereof. The terminating resistances of the networks are the resistances produced by a pair of differentially controlled thermistors. A DC error signal that is proportional to line length controls the current driving the thermistors and thus the resistances thereof. When the circuit arrangement is at half-span spacing, a difference circuit causes the terminating resistances of the thermistors to be the same values, which make the impedance characteristics of the networks such that the net gain of the amplifier is flat.

Abstract: A circuit for use with a transformer having a plurality of windings monitors the direct current flow through a first winding and provides a corresponding compensation current to a second winding. The circuit also provides an output signal indicating whether the magnitude of the compensation current is greater than or less than a predetermined magnitude.

Abstract: A composite test signal consisting of a search test signal and a sweep test signal from a link test set is combined with the through-path traffic signals during in-service testing. The composite signals are simultaneously applied to a transmitter of a microwave radio communication link under test. The sweep signal level is adjusted at the microwave radio communication link transmitter so that the total FM deviation is limited to the normal IF or RF transmission frequency band. The composite test signals and traffic signals are received and split into a through path signal and a test path signal. In the through path, the test signals are blocked, and the traffic signals are transmitted to the next microwave radio hop. In the test path, the traffic signals are blocked, and the test signals are applied to the receive section of a link test set. The link test set is then used to measure the transmission characteristics of the microwave radio communication link under test.

Abstract: In a digital communication system, apparatus for upconverting the bit rate, f.sub.1, of a digital data source to permit digital transmission at a bit rate f.sub.2, where f.sub.2 > f.sub.1. Pulse stuffing techniques are used to insert a fixed number of time slots in the digital data signal such that the ratio of information time slots to stuffed time slots remains constant. The upconverted signal, consisting of nonredundant data bits and stuffed time slots, is interleaved with framing bits prior to transmission over a digital facility. The framing bits provide the synchronization information to enable the receiver to identify the added time slots and to selectively remove the information data bits from the transmitted line signal. The desired data bits are then restored to their original f.sub.1 bit rate.

Abstract: A magnetic latching reed switch bobbin is wound on an automatic coil winding machine with a single polyurethane insulated wire by employing a bobbin having a base at one end with an extra terminal post mounted thereon in addition to the four terminals required for the primary and secondary coils and their associated contact pins, initially securing the end of the coil wire to a primary coil terminal, winding a bottom primary coil in a counterclockwise direction in a bottom coil compartment adjacent the base, connecting the wire to the extra terminal, feeding the wire to an adjacent secondary coil terminal so as to form a strap between the two terminals, winding in a counterclockwise direction a bottom secondary coil over the bottom primary coil, feeding the wire across a flange separating bottom and top coil compartments and housing a shunt plate assembly, winding a primary coil in a clockwise direction in the top coil compartment, returning the wire across the shunt plate assembly and across the previously w

Abstract: A conference arrangement for use in a pulse code modulated system including first and second control memories and a comparison logic circuit. Two words corresponding to two channels are read from information memory during each time slot and after proper comparison, the largest sample is transmitted to a third channel. Also included is a dial tone source for supplying dial tone to all terminations in the system by writing a time slot number assigned to the dial tone source and the respective ones of the channel memory words in the control memory associated with the channels.

Abstract: A method of providing a multi-port conference circuit for use in a telephone switching system employing pulse coded modulated signals for transmission and supervision. Samplings of coded information are employed as a source of conference data and comparison with the digital information contained therein is employed to choose the speaker in a conference group.

Abstract: A parity checking circuit for use in multifrequency tone receivers is disclosed wherein associated receivers are made less susceptible to digit simulation when talking is present, by verifying that the same two tones are present for the entire parity timing period.

Abstract: A computer memory control arrangement includes a plurality of input/output ports for permitting a central processor connected to one port to access a main memory to obtain/or store data or instructions for enabling the central processor to effect call processing or maintenance operations and for permitting the transfer of other programs to the main memory from a drum control memory including at least one drum control unit connected to a further port. A port select circuit permits port selection on a priority basis when memory requests are received over more than one port simultaneously. In addition, while the memory request for a selected port is being processed, the selection of a second port for a second memory request can be initiated before the end of the memory cycle for the first selected port. Each drum control unit has an assigned block of data storage locations or an initialization table of any computer main memory.

Abstract: Matched voltage-controlled resistances are provided across the drain-to-source channels of a pair of FET's, each FET having a gate electrode connected through an associated control resistor to the same one terminal of a source of DC control voltage; having a source electrode electrically connected to the same other terminal of the voltage source; and having an associated feedback resistor electrically connected between its drain and gate electrodes. The drain electrodes are preferably capacitively coupled to input or output terminals to prevent DC loading of the FET network by external circuitry. A resistor is also connected across the drain-to-source channel of each FET to limit the maximum value of net resistance presented thereby. The resistance of one of the control resistors is adjusted to have a value which causes the net drain-to-source resistance of the associated FET to have the same value as that of the other FET for a particular value of control voltage.

Abstract: In this test set, each one of a pair of resistive bridges has one node thereof connected to ground, one of the arms of each bridge that is adjacent the one nodes being open. Each one of a pair of ungrounded terminals of a balanced circuit under test is connected to a different one of the ungrounded nodes associated with the open arms of the bridges. Any center ground terminal of the test circuit is connected to the one nodes, which are grounded. Equal amplitude test signals of the same phase are applied to the pair of nodes on the two bridges that are adjacent to the one nodes thereof. A reflected signal coupled from the pair of nodes on the two bridges that are opposite the one nodes thereof is applied to a VTVM which provides an indication of the return loss of the test set, in relation to the individual bridge resistances which are the same values.

Abstract: A circuit for electronically generating chime-like tones wherein an oscillator circuit output is passed through a diode bridge having another diode across the D.C. terminals thereof and poled to be conductive. The resultant tone is distorted to considerably increase its harmonic content. Further to obtain the desired decoy characteristics a capacitor is included in series with said other diode to thus decrease the current through said bridge as the capacitor becomes charged.

Abstract: Gain control circuits associated with the base and emitter electrodes of a common-emitter transistor amplifier stage include pluralities of electrically conductive screw-type switches and resistors. The net gains provided by the associated gain control circuits are cumulative and determine the net gain of the stage. The gain changes provided by individual switches of the base and emitter gain control circuits are also cumulative, the switches being selectively closed in a prescribed manner to provide step changes in the decibel value of the net gain of the stage in discrete steps of the same magnitude. A plurality of transistor amplifiers with associated emitter gain control circuits may be connected in series, with the decibel values of voltage gains thereof also being additive, to provide additional steps and range of voltage gain. Series resistors in the base gain control circuit are selectively short-circuited by screw switches to decrease the input resistance of the amplifier stage.

Abstract: In a digital multiplexer which employs pulse stuffing and a plurality of signaling bits including evenly spaced framing bits, a framing circuit consists essentially of a pair of flip-flops which store the last values of a winking framing signal or the error signal which may have occurred during the framing time slots. Outputs of the flip-flops are connected to gating circuits. One said gate produces an output signal when an error occurs. This error signal is applied to an error density detector. When an out-of-frame condition occurs, i.e., the receiving circuit is considered not to be synchronized with the transmitting circuit, the error density detector output which is applied to a clock pulse generator causes an extended count to occur for each error occurrence. This offsets the bit stream by one time slot for each error following the out-of-frame condition, and this extended count follows the extended count due to the presence of a signaling bit.

Abstract: An arrangement and method for providing a dial pulse muting function to prevent the sender outpulsing from being heard is to disable the sampling of the transmit to the network side of the trunk circuit which is connected through the time switch and to the receiver from the network side of the line circuit. This function takes place in the trunk circuit, rather than the line circuit, so that less equipment is required. The function, furthermore, is provided through the use of integrated circuit chips as opposed to relays so that less space is required and the arrangement is far more reliable.

Abstract: An automatic call transmitter which uses a dual tone multifrequency generator first under the control of a pushbutton set to record, on a recording medium, a series of dual tones corresponding to a telephone number to be called, and which then uses this generator to regenerate pairs of voice frequencies corresponding to the recorded dual tones, under the control of switching means rendered frequency responsive by associated tuning means and selectively operated from the recorded tones upon playback to transmit the telephone number over a line. The automatic call transmitter may be in the form of a telephone reporting unit and the recording medium, such as an endless magnetic tape wound on a cartridge may also be used for recording and/or transmitting an oral message.

Abstract: A self-balancing telephone-type hybrid having two sets of conjugate ports, wherein conjugacy is maintained between receiving and transmitting ports despite wide variations in impedance conditions at the line and/or balance ports. Included are means of differentiating between bridge unbalance due to impedance unbalance and that due to a signal being injected into the line port.