Abstract: Simplified CCIS (Common Channel Interoffice Signalling) data transfer circuitry is shown for transmitting data between a CCIS central processing unit of a central switching office and a number of terminal equipment controllers, each having a local CPU. The terminal equipment controller operates such equipment as modems of various speed, digital trunks or T1 spans. This design minimizes the amount of circuitry required to transmit CCIS data between central processing units, thereby permitting a more reliable design. This circuit provides a minimal amount of logic required for interprocessor communication. In addition, this circuit minimizes the amount of real time required by each CPU to perform the CCIS data transfer.

Abstract: An arrangement for splicing and aligning two fiber optic cables is disclosed comprising a fixed connector stage and a movable connector stage. The fixed connector stage includes a fiber optic connector having a first fiber optic cable mounted therein. The first fiber optic cable has one of its ends connected to a source of light energy. The movable connector stage also includes a fiber optic connector having a second fiber optic cable housed therein. The two connector stages are located adjacent to the other with the two optical fibers coarsely aligned alog a horizontal axis. An alignment fixture is then mounted to the movable connector stage and an end of the second fiber optic cable connected to a photo-detector device. The light detector is electrically connected to a control device with the control device in turn electrically connected to the alignment fixture.

Abstract: An interface circuit for transmitting data messages between a CENTREX equipped central office exchange and a remotely located attendant console. The interface circuit includes control and sense decoding circuitry arranged to output control signals to the interface circuit and transfer control signals and data messages to the CENTREX. Sequential memory connected to the control and sense decoding circuitry receives and stores from the CENTREX data messages responsive to an enabling signal from the CENTREX. The control and sense decoding circuitry signals a controller connected to the sequential memory that data messages have been loaded in the sequential memory. The controller then transfers the data messages out of the sequential memory and processes the received data messages, storing the data messages in a temporary memory. The controller transfers the data messages from the temporary memory to sending circuitry which transmits the data messages to the attendant console.

Abstract: An arrangement for initializing an interface circuit connected between a CENTREX equipped central office exchange and a remotely located attendant console. The arrangement includes an operating unit residing in the interface circuit. The operating unit includes a controller connected to memory and to the CENTREX. The controller receives an initialization signal from the CENTREX and returns an initialization in progress signal. Memory verification called next by the controller ascertains if all locations in the memory are operable. The controller sends an error signal to the CENTREX in the event the memory verifications detects an error. Next, interface initialization called by the controller resets and clears a sequential memory and resets and clears a send/receive circuit connected to the controller and the attendant console. Transmission verification called next by the controller checks if the transmit and receive loop between the attendant console and the interface circuit is operable.

Abstract: An interface circuit for transmitting data messages between a remotely located attendant console and a CENTREX equipped central office exchange. The interface circuit includes control and sense decoders connected to control and sense fields. Receiving circuit connected to the attendant console receive data messages transmitted from the attendant console. A controller connected to the receiving circuit process the received data messages, storing the data messages in a temporary memory. Sequential memory connected to the temporary memory receive and store in sequential order the data messages after they are processed. The sequential memory further includes memory enabling circuit connected to the control and sense decoder.

Abstract: An arrangement for tranmitting data messages between a remotely located attendant console and a CENTREX equipped central office exchange. The arrangement includes an operating unit residing in an interface circuit connected between the attendant console and the central office exchange. The operating unit of the present invention includes receiving circuitry connected to the attendant console and to a controller. The receiving circuitry is arranged to receive a data message from the attendant console and set a receive signal. A state machine called by the controller transfers the first byte of the data message to a temporary memory and resets the receive signal. The state machine accepts all additional characters from the receiving circuitry storing received characters in the memory until a character sequence is received indicating the end of the data message. When a complete data message is received an analysis is called by the controller which analyzes the received data message.

Abstract: A synchronizing circuit that synchronizes the non-maskable interrupt (NMI) input signals of two separate microprocessor subsystems that are running synchronously as part of a fault tolerant computer system. This circuit enables both microprocessors to detect and respond to an error condition at an identical point in their relative bus timing sequence even though there may be a real time skew between the bus timing of these two subsystems. Storage and gating circuitry are used to provide the precise timing signals required for such synchronization.

Abstract: A synchronizing circuit synchronizes the asynchronous ready signals for two separate microprocessor subsystems that are running synchronously as part of a fault tolerant computer system. Duplicated synchronization circuits, confined in a master-slave arrangement, are utilized with the duplicate microprocessors. Storage and gating circuitry are used to provide the precise timing signals required for such synchronization.

Abstract: A differential amplifier feedback current mirror includes a feedback current source that provides a correction current to one input of a differential amplifier. The correction current is synthesized by comparing a sample of the current delivered by a string of controlled current sources to a reference current set up by a constant current source. A current driver is included in the differential amplifier feedback loop and a current source buss is driven by the current driver. The feedback configuration assures that the current delivered by the dependent controlled current sources accurately tracks the current established by the reference current source, irrespective of the base current offset attributable to each of the dependent controlled current sources.

Abstract: This circuitry expands the memory addressing arrange of a microprocessor beyond its directly addressable memory capacity. This circuit uses the status outputs of the microprocessor to segregate memory accesses for program code instructions from accesses for other data. This segregation scheme assigns different memory banks to program code instructions and to data. Memory reads and writes for scratch pad data are performed from one bank of memory. Memory reads for program code instructions are performed from a separate memory bank. This memory bank technique can double the size of a microprocessor's directly addressable memory without changing the microprocessor's architecture. This circuitry is suitable for implementation with CMOS gate array technology.

Abstract: A circuit adds and subtracts pulse code modulation (PCM) samples in D2 format. An exponent subtractor determines the difference between exponents of the two PCM samples. A mantissa shifter circuit shifts the mantissa portion of a selected PCM sample to compensate for the difference in the exponents. A mantissa adder circuit adds or subtracts the mantissa portion of the shifted and unshifted PCM samples and a sign generator provides a sign value representative of the resultant added or subtracted PCM samples. A normalizer circuit ensures that the mantissa has a predetermined range of values.

Abstract: A method of adjusting and testing for proper operation a current sensor by applying a threshold current value to the current sensor and adjusting the current sensor to a point just past the threshold of operation. Proper operation of the current sensor is tested by applying a non-operate current value followed by an operate current value to the sensor and checking for respective non-operate and operate output signals from the sensor. Messages, pass/fail indication, and audio signals are provided to signal test results to an operator.

Abstract: An apparatus for testing current sensors employing an electromagnetic coil and one or more Hall Effect switches including a microprocessor controlling a constant current source and visual and audio indicating circuits. A parameter input circuit is provided to permit an operator to select device types and to select test only, or adjustment and test sequences to be executed. The constant current source is adapted to apply a threshold, must-not-operate, and a must-operate current values to the electromagnetic coil. The visual and audio indicating circuits are adapted to provide messages, pass/fail indications, and audio signals signaling test success or failure results to an operator.

Abstract: This invention discloses a circuit for examining the value transmitted via a digital bus. A determination is made as to whether the value matches a predefined programmable value. An output indication is given for a match. In addition, this circuit may examine the transmitted value to determine whether it is within the bounds of a predefined range of values. This circuit utilizes a minimum of space and hardware components, due to its fabrication using RAM devices and a program logic array.

Abstract: Cable brackets are formed out of wire and have flat areas swaged into them to provide suitable mounting surfaces. The wire is of sufficient diameter to provide structural rigidity to the bracket and the flattened areas are of such dimension to provide an area sufficiently large enough for a mounting hole.

Abstract: A control circuit for effecting the transfer of data messages between an interface circuit and a CENTREX equipped central office exchange. The central office exchange includes a peripheral processor and the interface circuit includes an input and an output sequential memory for receiving and sending respectively, data messages to the peripheral processor. An input control circuit includes a first gating means having inputs connected to the peripheral processor and which produces an output signal responsive to the simultaneous application of a first and a second control signal. First bistable memory means receives the gating means output signal and further includes a clock input connected to a write select signal from the peripheral processor. Responsive to the write select signal, the gating means output signal is stored in the first bistable memory means. Second bistable memory means connected to the first bistable memory means output includes a clock input connected to a source of clocking signals.

Abstract: A method of coding a ROM from a partially processed semiconductor wafer comprising a substrate, a plurality of spaced regions separated by regions of isolating oxide deposited in said substrate, a layer of gate oxide overlying each of said spaced regions and a gate electrode overlying each layer of said gate oxide, is described comprising the use of photoresist material for preventing the formation of source and drain regions under selected ones of said gate electrodes during a subsequent doping step. The photoresist material restricts the area of implantation of dopant used for forming source and drain regions in the ROM device.

Abstract: An integrated circuit which facilitates measurement of various integrated circuit packaging parameters, including atmospheric moisture content, impurity content, water vapor transmission rate of encapsulant, corrosion of metallization, temperature, thermal impedance, and strain sensing. This circuit can be interconnected via both wire bonding and mass bonding, and it functions as a test vehicle for the tape automated bonding process. This circuit includes a plurality of subcircuits arranged in a square array such that the test capabilities of both the complete circuit and each individual subcircuit is identical.