Abstract: Disclosed are a hole connecting layer manufacturing method, a circuit board manufacturing method and a circuit board. The hole connecting layer manufacturing method comprises: adhering a first insulating dielectric layer, used for laminating and filling, to a daughter board; laminating and solidifying the first insulating dielectric layer on the daughter board; adhering a second insulating dielectric layer, used for laminating and filling, to the first insulating dielectric layer which has been laminated and solidified; manufacturing a first receiving hole on the first insulating dielectric layer and a second receiving hole on the second insulating dielectric layer, wherein the first receiving hole and the second receiving hole are provided vertically opposite to each other; filling both the first receiving hole and the second receiving hole with a conductive medium to complete manufacturing of the hole connecting layer.

Abstract: Provided is a method for improving the corrosion resistance of a gold finger, which is applicable to an electro-optical circuit board including gold fingers, wherein a guide line is arranged at a root portion of the gold fingers of the electro-optical circuit board. The method comprises the following steps in sequence: 1) electrical connection: using an outer lead to electrically connect all gold fingers of a electro-optical circuit board; 2) solder resistance: performing solder resistance on an area other than the outer lead; 3) gold plating on the gold fingers; 4) etching of the outer lead; and 5) solder resistance: performing solder resistance on a vacancy after etching of the lead. In the method, an outer lead is arranged to electrically connect all gold fingers of a electro-optical circuit board, so that all sides of the gold fingers are plated with gold, thereby significantly improving the corrosion resistance of the gold fingers.

Abstract: A printed circuit board (PCB) panelization method and a PCB panelization system are disclosed herein. The PCB panelization method comprises the following steps: S1, reading daughterboard information of purchase orders, wherein the daughterboard information comprises respective areas, delivery quantities and attributes of daughterboards; S2, performing comparison of the daughterboard information, screening for daughterboards having attributes that are the same, and establishing a panelization rule database; S3, selecting panels (PNLs) satisfying requirements according to panelization requirements; S4, selecting, from the daughterboards having the same attributes as the selected panels, daughterboards to be panelized together for the selected panels, and arranging a graphical layout for a panelization of the selected panels.

Abstract: Disclosed is a method for performing netlist comparison based on a pin connection relationship of a component, comprising the steps: acquiring a schematic diagram netlist file generated by a schematic diagram, and acquiring a PCB netlist file generated by a PCB; reading a network in the schematic diagram netlist file, forming a netlist connection relationship corresponding to each network into a schematic diagram array, all schematic diagram arrays forming a schematic diagram array set; reading a network in the PCB netlist file, forming a netlist connection relationship corresponding to each network into a PCB array, all PCB arrays forming a PCB array set; and comparing the schematic diagram array set with the PCB array set, and outputting differences between the two array sets. The present disclosure merely compares the connection relationship of components.

Abstract: Provided is a differential wiring method for a high-speed printed circuit board, including the following steps: setting a pre-set impedance required value Z2 of a non-ball grid array (BGA) region, determining the width w2 of the second differential wire and the distance d2 between the two second differential wires according to the pre-set impedance required value Z2; calculating the width w1 of the first differential wire and the distance d1 between the two first differential wires, according to the distance s1 between two adjacent rows of bonding pads in a BGA region bonding pad array and the minimum processable distance s2 between the bonding pad and the first differential wire, where w1 and d1 should satisfy 2w1+d1?s1?2s2, while further calculating w1 and d1 according to a differential characteristic impedance formula; arranging the two first differential wires disposed oppositely to each other in the BGA region according to the determined d1, and arranging the two second differential wires disposed opposi

Abstract: Provided is a method for improving the corrosion resistance of a gold finger, which is applicable to a photovoltaic panel (1) including gold fingers (2), wherein a guide line (3) is arranged at a root portion of the gold fingers (2) of the photovoltaic panel (1). The method comprises the following steps in sequence: 1) electrical connection: using an outer lead (4) to electrically connect all gold fingers (2) of a photovoltaic panel (1); 2) solder resistance: performing solder resistance on an area other than the outer lead (4); 3) gold plating on the gold fingers (2); 4) etching of the outer lead (4); and 5) solder resistance: performing solder resistance on a vacancy after etching of the lead (4). In the method, an outer lead (4) is arranged to electrically connect all gold fingers (2) of a photovoltaic panel (1), so that all sides of the gold fingers (2) are plated with gold, thereby significantly improving the corrosion resistance of the gold fingers (2).

Abstract: A printed circuit board (PCB) panelization method and system. The method comprises the following steps: S1, reading daughterboard information of purchase orders, wherein the daughterboard information comprises the respective areas, delivery quantities and attributes of daughterboards; S2, performing comparison of the daughterboard information, screening for daughterboards having the same attributes, and establishing a panelization rule database; S3, selecting panels (PNL) satisfying the requirements according to panelization requirements; S4, selecting, from the daughterboards having the same attributes as the selected panels, daughterboards to be panelized together for the selected panels, and arranging the layout for the panelization.

Abstract: Provided is a differential wiring method for a high-speed printed circuit board, including the following steps: setting a pre-set impedance required value Z2 of a non-ball grid array (BGA) region, determining the width w2 of the second differential wire (210) and the distance d2 between the two second differential wires (210) according to the pre-set impedance required value Z2; calculating the width w1 of the first differential wire (110) and the distance d1 between the two first differential wires (110), according to the distance s1 between two adjacent rows of bonding pads in a BGA region bonding pad array and the minimum processable distance s2 between the bonding pad and the first differential wire (110), where w1 and d1 should satisfy 2w1+d1?s1?2s2, while further calculating w1 and d1 according to a differential characteristic impedance formula; arranging the two first differential wires (110) disposed oppositely to each other in the BGA region according to the determined d1, and arranging the two secon

Abstract: Disclosed is a method for performing netlist comparison based on a pin connection relationship of a component, comprising the steps: acquiring a schematic diagram netlist file generated by a schematic diagram, and acquiring a PCB netlist file generated by a PCB; reading a network in the schematic diagram netlist file, forming a netlist connection relationship corresponding to each network into a schematic diagram array, all schematic diagram arrays forming a schematic diagram array set; reading a network in the PCB netlist file, forming a netlist connection relationship corresponding to each network into a PCB array, all PCB arrays forming a PCB array set; and comparing the schematic diagram array set with the PCB array set, and outputting differences between the two array sets. The present disclosure merely compares the connection relationship of components.

Abstract: Disclosed is a drilling method for PCBs with high hole position precision, comprising: step 1 of fixing a PCB on a workbench; step 2 of pre-drilling a to-be-drilled portion of the PCB by using a short-blade drilling tool; and step 3 of deeply drilling the to-be-drilled portion which has been machined in step 2 by using along-blade drilling tool.

Abstract: A boss-type metal-based sandwich rigid-flex board and preparation method thereof are disclosed. The boss-type metal-based sandwich rigid-flex board comprises a rigid sub-plate, a flexible sub-plate, a dielectric layer, and a metal core layer, wherein the metal core layer has front and back sides on which at least one metal boss and at least one heat dissipation area are arranged respectively, the dielectric layer, and the rigid sub-plate and/or the flexible sub-plate are sequentially stacked on the front and back sides of the metal core layer respectively, and each of the rigid sub-plate, the flexible sub-plate and the dielectric layer is provided with a first window area fit with the metal boss, and a second window area corresponding to the heat dissipation area. The boss-type metal-based sandwich rigid-flex board (with a metal boss and a heat dissipation area arranged on the front side) prepared according to the present disclosure uses a metal core layer for heat dissipation.

Abstract: Provided is a method for manufacturing a rigid-flexible circuit board having a flying-tail structure, comprising the following steps: step 1: manufacturing core substrates needed by daughter boards (500), the cord boards needed by each daughter board comprising at least one flexible core substrate (510) and at least one rigid core substrate (520), stacking and laminating the core substrates to manufacture daughter boards, the number of the manufactured daughter boards being equal to the number of second rigid areas (300), and each daughter board comprising a partial first rigid area (110), a flexible area (200), and a second rigid area (300); step 2, stacking the daughter boards obtained in step 1, and pasting polyetherimide covering films (400) on solder-resist areas of adjacent end surfaces of the second rigid areas; and step 3, providing PTFE gaskets (600) between adjacent flexible areas and adjacent second rigid areas, laminating the daughter boards that have been processed in step 2, and laminating the p