Abstract: A measurement of phase frequency response of a device under test (DUT), wherein the DUT is characterized by a set of switchable configurations, comprises choosing the steps of a particular configuration of the DUT having nominal parameters as a reference configuration, measuring an amplitude frequency response Aref (f) and a phase frequency response ?ref(f) of the reference configuration, processing all configurations of the DUT which are different from the reference configuration, one after another, by measuring an amplitude response A(f) of the configuration being processed, calculating a minimum phase difference response ??min(f); and calculating for each configuration, a phase frequency response ?(f) of the respective configuration which is being processed, in accordance with ?(f)=?ref(f)+??min(f).

Abstract: A measurement of phase frequency response of a device under test (DUT), wherein the DUT is characterized by a set of switchable configurations, comprises choosing the steps of a particular configuration of the DUT having nominal parameters as a reference configuration, measuring an amplitude frequency response Aref (f) and a phase frequency response ?ref(f) of the reference configuration, processing all configurations of the DUT which are different from the reference configuration, one after another, by measuring an amplitude response A(f) of the configuration being processed, calculating a minimum phase difference response ??min (f); and calculating for each configuration, a phase frequency response ?(f) of the respective configuration which is being processed, in accordance with ?(f) =?ref(f)+??min(f).

Abstract: Repetitive waveforms are processed to produce an averaged replica of the waveforms by first determining a stream of digital samples, with random time shifts of waveform starts relative to the samples. A mutual arrangement of a trigger signal and a following sample over a succession of sampling periods, enables k sections coinciding with segments [k·T/K, (k+1)·T/K]. K is determined and a distance D between the trigger signal and the following sample is calculated. Second, values of the samples are transformed so that waveforms represented by the samples, are shifted in time by D in relation to the sample positions. The mutual positions of the delayed waveforms and the sampling clock along multiple axes, exactly repeats so that values of the produced samples along the axes coincide. The discreet time delays before averaging avoid frequency component distortions in resulting replicas of the waveforms.

Abstract: A broadband digitizer for an applied broadband analog input signal SA(t). The digitizer includes a low frequency analog-to-digital converter (LF ADC) channel and a high frequency analog-to-digital converter (HF ADC) channel, an input splitter coupled to respective inputs to the LF ADC channel HF ADC channels, a frequency divider, and a combining unit. Low frequency portions of SA(t) are digitized to digital signal SDLF[n] in the LF ADC channel and high frequency portions of SA(t) are digitized to digital signal SDHF[n] in the HF ADC channel. The combining unit combines the digital signals SDLF[n] and SDHF[n] to form distortion-reduced SD[n], corresponding to SA(t). Front ends of the LF ADC channel and HF ADC channel reduce level-caused distortions, and the combining unit reduces ADC frequency-caused, time-position-caused, and interpolation-caused distortions.

Abstract: A real time digital trigger detection channel includes an event detector, a pulse former, a low pass filter, an analog-to-digital converter (ADC) and a Discrete Fourier Transform (DFT) processor coupled in series. The event detector is responsive to an applied input signal and the presence of information requiring digital trigger generation. The pulse former generates a pre-determined, limited length, stable pulse signal which is applied to an anti-aliasing, pulse shaping low pass filter. The resultant shaped pulse signal is converted to a sequence of sample values by the ADC, which in turn are applied to the DFT processor, which in turn calculates a discrete Fourier transform of the output sequence of ADC samples, performing trigger position calculation based on values determined by the DFT processor.

Abstract: Noise suppression is achieved by averaging a sequence of repetitive waveforms with correction of frequency distortions, establishing a real time processing of signals. First, the waveforms are processed seriatim, and saved in partitioned memory. Then, the memory contents are merged to form an output digital signal. Initially, an input repetitive signal is sampled with a sampling period T, and divided into K sections along the sampling period so that a kth section, where 0?k<K, coincides with segment [k·T/K, (k?1)·T/K]. Time displacement detection determines relative positions of trigger pulses and edges of the sampling clock, and the number k of a sampling period section where the trigger pulse appears, keeping k unchanged thereafter. A resultant stream of N·K samples is transmitted through a lowpass filter, followed by decimation by K, to complete the averaging.

Abstract: A digital equalizer with reduced number of multipliers for correction of the frequency responses of an interleaved analog-to-digital-converter (ADC) is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes at least one composite ADC including M time-interleaved sub-ADCs, and an equalization configuration deploying a Pre-FIR transformers unit, a FIRs assembly unit, and a Post-FIR transformers unit. The FIRs assembly unit includes a finite impulse response (FIR) filter network which is operative pursuant to a Fast Filtering Algorithm as an alternative to a conventional finite impulse response network, enabling a reduction of the number of multipliers compared to conventional FIR filter-based equalization networks for ADCs.

Abstract: A method and apparatus for resolving time base-generated errors from sampling scope-based measurements. Mutually synchronized repetitive waveform-to-be-analyzed signals (WAS) and repetitive sinusoidal reference signals (RS) are respectively applied to a first channel and a second channel of a sampling scope. A time base generator applies a sampling signal to the first and second channels. An average sine wave period Tav for k samples of RS is determined, followed by determination of phase error ?k for each of the k samples, corresponding to phase differences between an ideal sine wave signal and the applied reference sinusoidal signal. Time base error values dk for k samples are calculated from dk=?k*Tav/2?. Error values dk correct time base errors in the sampling signal, and the WAS is re-sampled at sampling times adjusted by dk.

Abstract: A method and system for calibrating a time-interleaved digital to analog converter (DAC) provides equalization of frequency response misalignments in sub-DACs forming the DAC. In a calibration mode, test signals are applied to an DAC and output amplitudes and phases of are measured. From the measured values, complex values of the gains of the respective sub-DACs. hm(F) are determined and a specified target frequency response T(F) for a tandem connection equalizer-DAC is determined. For each of a plurality of test frequencies, complex values of equalizer gains Eqm are determined from Eqm(F)=T(F)/hm(F), to form equalizing frequency responses. Sets of equalizing coefficients Cm(p) pursuant to discrete Fourier transforms on Eqm(F). In an operation mode, a digital input signal is transformed input into an equalized digital signal E(n) through use of the sets of equalizing coefficients Cm(p).

Abstract: A digital down-converter with baseband equalization comprises a composite analog-to-digital converter (ADC) adapted to convert an applied RF analog signal to be processed to a digital signal, and then down-convert the digital signal to a baseband frequency region, and then perform equalization on the down-converted digital signal, thereby reducing distortions caused by introduction of spurious signals by the ADC.

Abstract: A unitary cartridge, or module, provides a self-contained, high accuracy, ready-to-use assembly for controlling fine positioning of a head gimbal assembly (HGA) disposed on a head mounting unit mounted on the cartridge, with respect to a spinstand or other device associated with a head tester. In a form, the head-mounting unit and a counterweight element are configured to be moveable relative to the base in opposite directions along a displacement axis in response to actuators in the cartridge, and are operative in concert with a damping assembly configured to interact with the counterweight element and the heads mounting unit to mitigate vibrational movement of the cartridge.

Abstract: Measurement of group delay for a device under test (DUT). A test signal includes (i) a low frequency sine wave fLF, (ii) sine wave harmonics at a high frequency fHF, (iii) L pairs of sideband components at frequencies k·fHF±2·fLF, where k odd, and M pairs of sideband components at frequencies k·fHF±fLF, where k is even. At DUT output, (i) phase ?LF at frequency fLF is measured, (ii) both sideband phase ?right(k) at frequencies k·fHF+2·fLF and phase ?left(k) at frequencies k·fHF?2·fLF for odd k, are measured, and (iii) both sideband phases ?right(k) at frequencies k·fHF+fLF and ?left(k) at frequencies k·fHF?fLF for even k, are measured. Group delay ?k at frequencies k·FHF, are determined from: ?k=(?right(k)??left(k)?4·?L)/(4·fLF) for k odd, and ?k=(?right(k)??left(k)?2·?L)/(2·fLF) for k even.

Abstract: Measurement of group delay for a device under test (DUT). A test signal includes (i) a low frequency sine wave fLF, (ii) sine wave harmonics at a high frequency fHF, (iii) L pairs of sideband components at frequencies k·fHF±2·fLF, where k odd, and M pairs of sideband components at frequencies k·fHF±fLF, where k is even. At DUT output, (i) phase ?LF at frequency fLF is measured, (ii) both sideband phase ?right(k) at frequencies k·fHF+2·fLF and phase ?left(k) at frequencies k·fHF?2·fLF for odd k, are measured, and (iii) both sideband phases ?right(k) at frequencies k·fHF+fLF and ?left(k) at frequencies k·fHF?fLF for even k, are measured. Group delay ?k at frequencies k·FHF, are determined from: ?k=(?right(k)??left(k)?4·?L)/(4·fLF) for k odd, and ?k=(?right(k)??left(k)?2·?L)/(2·fLF) for k even.

Abstract: A piezoelectric actuator includes a housing body and lid wherein the housing body defines an open-ended cylindrical interior chamber extending along a displacement axis. The lid bolts to the body transverse to the open end allowing easy access to an electrostrictive assembly disposed within the chamber. The electrostrictive assembly includes an electrostrictive element affixed at one end to the housing by a cup element with an outermost cylindrical surface, and at an opposite, and free, end, to a driver having a portion with a outermost cylindrical surface. The outermost cylindrical surfaces both include circumferential sealing elements, for example, circumferential grooves in which resilient a sealing O-ring resides, or circumferential wiper seals. The assembly is dimensioned to fit wholly within the chamber, with the circumferential sealing elements establishing a hermetic seal while allowing sliding motion of the free end of the electrostrictive element, and the driver, along the displacement axis.

Abstract: An HGA loader provides HGAs, in succession, to a multiple workstation head tester. An HGAs carrier station receives HGAs to be tested. An alignment station on the base includes an alignment surface which selectively rotates about an alignment axis. A camera generates images of an HGA on the alignment surface, which is rotated so that the HGA has a desired spatial orientation which is maintained as the HGA is transferred to an HGA testing workstation. A received, oriented HGA is positioned to enable read/write test operations on a disk rotating on an adjacent spinstand. To effect the successive position operations, a transporter includes a track overlying the workstations, and a carriage movable along the track, to pass from workstation to workstations. The loader is automatically operative under the control of a controller.

Abstract: A method and apparatus for processing a periodic analog signal using a composite ADC including a time interleaved set of sub-ADCs, to produce a replica signal representative of the analog signal, wherein the replica signal is characterized by suppression of additive noise on the periodic analog signal, and correction of sub-ADC-caused distortions. Streams of samples from the respective sub-ADCs are accumulated separately for respective positions in signal periods of the periodic analog signal to provide sub-replicas. Fourier transforms of the replicas are determined for the different sub-ADCs, and those Fourier transforms are averaged to obtain a mean Fourier transform. Frequency responses of the sub-ADCs are corrected by dividing the mean Fourier transform by the respective sub-ADC frequency responses. An averaged replica of the signal period is obtained by determining an inverse Fourier transform of the corrected mean Fourier transform.

Abstract: A digital down converter with an equalizer translates an ADC output signal to a low frequency spectral region, followed by decimation. All operations of correction of the processed signal are carried out with a reduced sampling rate compared with sampling rates of the prior art. Equalization is performed only in a frequency pass band of the down converter. The achieved reduction of the required computation resources is sufficient to enable the down converter with equalization to operate in a real time mode.

Abstract: A digital down converter with an equalizer translates an ADC output signal to a low frequency spectral region, followed by decimation. All operations of correction of the processed signal are carried out with a reduced sampling rate compared with sampling rates of the prior art. Equalization is performed only in a frequency pass band of the down converter. The achieved reduction of the required computation resources is sufficient to enable the down converter with equalization to operate in a real time mode.

Abstract: A digital down converter with equalization includes a composite ADC that performs demodulation of a received analog signal, converting the signal into in phase baseband signal and quadrature baseband signal. Equalization is performed to correct for misalignment of the frequency responses of the sub-ADCs in the composite ADC. In a form, ADC output signals are applied to a mixer array to frequency down-shift the digital form of the input signal, followed by digital filtering to effect convolutions of portions of the digital form of the input signal with a set of convolution coefficients determined so that the net processing is mathematically equivalent to down conversion with equalization. In another form, the ADC output signals are directly applied to a digital filter to effect both frequency down-shifting and convolutions, with filter coefficients determined so that the net processing is mathematically equivalent to down conversion with equalization.

Abstract: A driving circuit is configured to apply a drive signal to a first terminal of a drive piezoelectric actuator having a second terminal coupled to ground. In response, the drive piezoelectric actuator controls the position of a head in a head gimbal assembly. A reference piezoelectric actuator, characterized by dimensional and electro-mechanical properties substantially matching those of the drive piezoelectric actuator, is included in the driving circuit. The driving circuit controls the reference piezoelectric actuator so that a voltage is produced across the terminals of the reference piezoelectric actuator, wherein that voltage is proportional to the charge stored in the reference piezoelectric element. That voltage is transmitted through a buffer amplifier to the drive piezoelectric actuator where it creates in it a charge equal to the charge in the reference piezoelectric actuator.