Abstract: Digital signal acquisition system is triggered when an input waveform matches a known reference waveform. This is achieved by calculating a stream of error metric values defined as a sum of absolute values of differences between incoming and reference samples. An error metric is calculated using only byte operations, which is advantageous for hardware implementation. A waveform trigger is determined by a sample index corresponding to a minimum value of the error metric and corresponds to a best match between input and reference waveforms. A waveform trigger is used for synchronous averaging and estimating time domain noise voltage. A reference waveform updates in poor SNR conditions to provide robust estimates of time domain noise by reducing reference waveform jitter.

Abstract: An HGA loader provides HGAs, in succession, to a multiple workstation head tester. An HGAs carrier station receives HGAs to be tested. An alignment station on the base includes an alignment surface which selectively rotates about an alignment axis. A camera generates images of an HGA on the alignment surface, which is rotated so that the HGA has a desired spatial orientation which is maintained as the HGA is transferred to an HGA testing workstation. A received, oriented HGA is positioned to enable read/write test operations on a disk rotating on an adjacent spinstand. To effect the successive position operations, a transporter includes a track overlying the workstations, and a carriage movable along the track, to pass from workstation to workstations. The loader is automatically operative under the control of a controller.

Abstract: An apparatus for securing an HGA to a tester includes a housing with a cylindrical cavity disposed about an axis, and having, at its top end, a mounting surface with a central aperture, for receiving an HGA base plate with a boss hole of the HGA overlying the central aperture. Axially elongated clamp fingers, radially dispersed about a spreader pin, move along the axis between (i) a loading position with upper ends extending through and relatively far beyond the central aperture, and (ii) a clamping position with the upper ends disposed at or near the mounting surface. With an HGA on the mounting surface, and the clamp fingers at their loading position, the clamp fingers are driven downward, while simultaneously, the clamp fingers are driven outward by the spreader pin, and the clamp fingers engage boss hole edges, securing the HGA to the tester.

Abstract: A unitary cartridge, or module, provides a self-contained, high accuracy, ready-to-use assembly for controlling fine positioning of a head gimbal assembly (HGA) disposed on a head mounting unit mounted on the cartridge, with respect to a spinstand or other device associated with a head tester. In a form, the head-mounting unit and a counterweight element are configured to be moveable relative to the base in opposite directions along a displacement axis in response to actuators in the cartridge, and are operative in concert with a damping assembly configured to interact with the counterweight element and the heads mounting unit to mitigate vibrational movement of the cartridge.

Abstract: A two-stage digital down-conversion device for optimal detection of varying RF pulses incorporates a front end analog to digital converter (ADC), which samples an input RF signal and performs a first stage digital down conversion in wide bandwidth by means of two digital local oscillator multipliers, low pass filters and decimators. A stream of first stage quadrature I and Q samples is analyzed by a first stage I/Q processor. The I/Q processor generates an RF pulse trigger based on a first-stage envelope signal, center frequency and frequency span data which are used for a second stage narrow band digital down-conversion. The second stage digital down-conversion is based on mixing the first stage I and Q data samples with a second stage local oscillator, further low pass filtering and decimation using a second bandwidth.

Abstract: An apparatus for securing an HGA to a tester includes a housing with a cylindrical cavity disposed about an axis, and having, at its top end, a mounting surface with a central aperture, for receiving an HGA base plate with a boss hole of the HGA overlying the central aperture. Axially elongated clamp fingers, radially dispersed about a spreader pin, move along the axis between (i) a loading position with upper ends extending through and relatively far beyond the central aperture, and (ii) a clamping position with the upper ends disposed at or near the mounting surface. With an HGA on the mounting surface, and the clamp fingers at their loading position, the clamp fingers are driven downward, while simultaneously, the clamp fingers are driven outward by the spreader pin, and the clamp fingers engage boss hole edges, securing the HGA to the tester.

Abstract: An acquisition device includes an analog to digital converter (ADC) composed of multiple interleaved ADCs (sub-ADCs), which receives an analog signal which is converted to digital form. The digitized signal is processed seriatim by a pre-(or trigger-) equalizer, an acquisition memory and a post-(or memory) equalizer. In a calibration mode, frequency responses of the respective sub-ADCs are determined and trigger coefficients are determined for application to the trigger equalizer to effect a preliminary equalization of the digitized signal sufficient to permit operation of the trigger processor in an acquisition mode. Memory coefficients are determined based on residual frequency responses of the sub-ADCs, for application to the memory equalizer. A trigger processor is responsive to the trigger equalizer to select a subset of samples of the digitized signal for loading to the acquisition memory.

Abstract: An acquisition device includes an analog to digital converter (ADC) composed of multiple interleaved ADCs (sub-ADCs), which receives an analog signal which is converted to digital form. The digitized signal is processed seriatim by a pre-(or trigger-) equalizer, an acquisition memory and a post-(or memory) equalizer. In a calibration mode, frequency responses of the respective sub-ADCs are determined and trigger coefficients are determined for application to the trigger equalizer to effect a preliminary equalization of the digitized signal sufficient to permit operation of the trigger processor in an acquisition mode. Memory coefficients are determined based on residual frequency responses of the sub-ADCs, for application to the memory equalizer. A trigger processor is responsive to the trigger equalizer to select a subset of samples of the digitized signal for loading to the acquisition memory.

Abstract: Radially-coherent data reading from, and data writing to, a magnetic disk use non-coherently written synchronization signals on the disk. In a form, the radially-coherent data reading and writing is performed using a magnetic head/disk tester which includes a spinstand for supporting a spinning magnetic disk, a magnetic head assembly, a write channel network for generating a write data signal for application to a write element of the magnetic head, a read channel for receiving a read-back signal from a read element of the magnetic head assembly, and a signal processing system that analyzes a read-back signal from a disk and provides synchronization signals for radially-coherent data reading and data writing.

Abstract: Radially-coherent data reading from, and data writing to, a magnetic disk use non-coherently written synchronization signals on the disk. In a form, the radially-coherent data reading and writing is performed using a magnetic head/disk tester which includes a spinstand for supporting a spinning magnetic disk, a magnetic head assembly, a write channel network for generating a write data signal for application to a write element of the magnetic head, a read channel for receiving a read-back signal from a read element of the magnetic head assembly, and a signal processing system that analyzes a read-back signal from a disk and provides synchronization signals for radially-coherent data reading and data writing.

Abstract: An analog to digital conversion device with DC offset mismatch compensation comprises a composite analog to digital converter (ADC) consisting of N interleaved sub-ADCs, a DC offset accumulator, an averaging unit, a subtraction unit, and a compensation unit. The ADC generates a stream of digital samples corresponding to signal values at an analog input to the ADC. The digital stream is a combination of N partial signals produced by the respective sub-ADCs. The DC offset accumulator measures and stores DC offsets of the respective partial signals. The averaging unit calculates an average value of DC offsets of the respective N partial signals. The subtraction unit is responsive to the DC offsets of the respective partial signals and the average value of the DC offsets, to produce a signal representative of the differences between the values arriving at a DC offset input and the value arriving at an average value input.

Abstract: A digital down converter with equalization includes an analog to digital converter (ADC), a frequency divider, an FIR-decimator-I, an FIR-decimator-Q and a frequency corrector. In operation, after some preprocessing, the FIR-decimator-I performs signal transformation equivalent to a sequence of equalization, multiplication of the processed signal by a sine wave of a conversion frequency and low pass filtering, and the FIR-decimator-Q performs signal transformation equivalent to a sequence of equalization, multiplication of the processed signal by a sine wave of conversion frequency with a phase shift of 90° and low pas filtering. The transformed signals are applied to the frequency corrector, which provides a frequency shift of predetermined value with respect to a nominal carrier frequency of the applied analog input signal and generates an In-Phase output and a Quadrature output.

Abstract: A digital down converter with equalization includes an analog to digital converter (ADC), a frequency divider, an FIR-decimator-I, an FIR-decimator-Q and a frequency corrector. In operation, after some preprocessing, the FIR-decimator-I performs signal transformation equivalent to a sequence of equalization, multiplication of the processed signal by a sine wave of a conversion frequency and low pass filtering, and the FIR-decimator-Q performs signal transformation equivalent to a sequence of equalization, multiplication of the processed signal by a sine wave of conversion frequency with a phase shift of 90° and low pas filtering. The transformed signals are applied to the frequency corrector, which provides a frequency shift of predetermined value with respect to a nominal carrier frequency of the applied analog input signal and generates an In-Phase output and a Quadrature output.

Abstract: A synchronization system for initial setup of phases of local oscillators in a wireless receiver of a communication system characterized by transmission of data packets having a predetermined preamble consisting of M identical sections of L symbols followed by a single section of the same kind, multiplied by ?1, and wherein the wireless receiver is operative to perform decimation in an RF demodulator. The synchronization system includes a twofold correlator, an accumulator, a multiplier, a threshold comparator, a carrier phase former and a clock phase former, and operates at a decimated symbols frequency, and performs not only preamble detection, but also symbols clock phase detection together with carrier phase detection, while enabling the theoretically possible noise immunity.

Abstract: A data acquisition device incorporates a front end analog-to-digital converter (ADC), which is responsive to an applied analog input signal, sample that signal and provide digital data representative of the sampled signal. The digital data is applied to a data channel connected to a data acquisition memory, which stores data values representative of the sampled analog input signal. The digital data from the ADC is also applied to a real time a trigger channel connected to a composite function trigger equalizer and filter, a trigger processor and to a trigger memory. The trigger channel operates in real time to identify trigger events and store real-time trigger event occurrence signals in the trigger memory. A controller reads out the stored data values from the data acquisition memory by way of a data equalizer, in synchronism with corresponding real-time trigger event occurrence signals from the trigger memory.

Abstract: A synchronization system for initial setup of phases of local oscillators in a wireless receiver of a communication system characterized by transmission of data packets having a predetermined preamble consisting of M identical sections of L symbols followed by a single section of the same kind, multiplied by ?1, and wherein the wireless receiver is operative to perform decimation in an RF demodulator. The synchronization system includes a twofold correlator, an accumulator, a multipler, a threshold comparator, a carrier phase former and a clock phase former, and operates at a decimated symbols frequency, and performs not only preamble detection, but also symbols clock phase detection together with carrier phase detection, while enabling the theoretically possible noise immunity.

Abstract: An adjustable disk stabilizer for a spinstand having a spindle motor and spindle assembly for supporting and rotating a magnetic medium bearing disk. The spinstand is adapted to position a transducing (read/write) head adjacent to the magnetic medium. The adjustable disk stabilizer is attached to a stationary portion of the spindle assembly, and includes a mechanism to adjust height and alignment of a plate having a bearing surface opposite a non-magnetic-media-bearing undersurface of the disk. That bearing surface, in concert with the undersurface of the disk, establishes a supporting air bearing therebetween during rotation of the media-bearing disk. The adjustment mechanism enables easily-attained compensation for various disk-to-disk thicknesses and level imperfections of the bearing surface plate mounting, and enables precision alignment of the bearing surface of the plate to the surface of the disk opposite to the surface under test.

Abstract: A data acquisition device incorporates a front end analog-to-digital converter (ADC), which is responsive to an applied analog input signal, sample that signal and provide digital data representative of the sampled signal. The digital data is applied to a data channel connected to a data acquisition memory, which stores data values representative of the sampled analog input signal. The digital data from the ADC is also applied to a real time a trigger channel connected to a composite function trigger equalizer and filter, a trigger processor and to a trigger memory. The trigger channel operates in real time to identify trigger events and store real-time trigger event occurrence signals in the trigger memory. A controller reads out the stored data values from the data acquisition memory by way of a data equalizer, in synchronism with corresponding real-time trigger event occurrence signals from the trigger memory.

Abstract: A digital equalizer with a reduced number of multipliers for correction of the frequency responses of an interleaved ADC is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes a composite ADC including M time interleaved sub-ADC, a demultiplexer, samples repositioning unit, a first PreFIRs transformer, a second PreFIRs transformer, K double buffer FIR filters, a PostFIRs transformer, a samples sequence restoration unit, and a multiplexer, coupled in series and providing an equalized, frequency response-corrected output.

Abstract: An interleaved analog to digital converter with digital equalization includes a conversion-measurement-equalization unit and residual distortions reduction unit, and is operative in a calibration mode and converter mode. The conversion-measurement-equalization unit includes a composite ADC containing N sub-ADCs, equalizer, responses measurement unit and a coefficients calculator. The residual distortions reduction unit uses received measured frequency responses and equalizer coefficients, both from the conversion-measurement-equalization unit, as a base to calculate corrected frequency responses that are applied to the coefficients calculator for generation of equalizer coefficients for application to the equalizer.