Abstract: A buffer circuit which exhibits increased speed in transitions between binary states. A control transistor is coupled between a pull-up transistor and an input terminal. During low-to-high input signal transitions, the control transistor limits the signal swing at the input terminal such that small variations in the input terminal voltage result in larger voltage variations at the output terminal. During such transitions, the control transistor simultaneously decouples the input terminal from the pull-up transistor, thereby decoupling the input capacitance from the pull-up transistor. As a result, the speed with which the pull-up transistor can pull the output high is increased. As the number of input signal desired to be processed increases, the reduction in logic transition time becomes more significant. Some versions further include a pull-down transistor having a control terminal coupled to the gate of the pull-up transistor and to a power-down terminal.

Abstract: A method and apparatus are disclosed for detecting and correcting errors in the data stored within the entries of a memory table. Each time data is entered into the memory table, an error code generator generates a corresponding error code using the data. This error code is stored in the memory table along with the corresponding data. When an entry in the memory table is read out, an error detector receives the outputted data and its corresponding error code and processes the data and the error code to determine whether the outputted data contains any errors. If the outputted data contains any errors, the outputted data and error code are sent to an error correction unit. In response, the correction unit attempts to find single and double bit errors in the data by way of a compact and efficient computer program. If either a single or double bit error is found, the error correction unit corrects the error or errors to derive a set of corrected data.

Abstract: A memory is tested by subjecting the memory to three phases of testing. In the first phase, a first address in the memory is initialized by writing an initial set of data to the address. Then data is read from the address just written to and this data is modified to produce a set of modified data. The modified data is then written to another address in the memory. The steps of reading, modifying, and writing modified data back to the memory are repeated until all addresses in the memory have been written to. Thereafter, the data values stored in the memory are compared to a reference list of data values to determine whether the memory contains a detect. In phase two, the steps of phase one are repeated except that the first address in the memory is initialized by writing a set of data which is the complement of the initial set of data used in phase one. Phase two, in effect, complements the contents of each address in the memory to ensure that each cell in the memory is written with both a 0 and a 1.

Abstract: A novel third phase of CMOS domino logic is identified and used in the logic system of the present invention to store data. The use of this third phase in addition to the normally used precharge and logic evaluation phases, provides a logic structure of cascaded domino logic gates which are pipelined without intervening latches for memory storage. The memory storage function of the conventional latches being provided by the third logic phase. The novel approach requires that the functional inputs to this system have strictly monotonic transitions during the logic evaluation phase, and requires that the precharge signal must be active during only the precharge phase. Embodiments of the pipelined system according to the invention, are structured so that the output of the pipeline are fed back to the input of the pipeline to form an iterative structure. Such a feedback pipeline is viewed as a "loop" or "ring" of logic. The logic ring circulates data until the entire computation is complete.

Abstract: A system and method for transferring data between clock domains operating at substantially the same frequency continuously compares the phase relationship of the clocks of the two domains and retains the current state of comparison at the start of a transfer of a block or frame of data for determining along which one of multiple data paths within the synchronizing circuit the transfer of the data frame will take place. Several data paths with different delays (at least two) transfer the data frame and clock signals. A phase comparator responds to the phase relationship between clocks attaining a value within one or another range of values at the start of a data frame to determine which one of the multiple data paths transfers the data frame.

Abstract: A memory is tested by subjecting the memory to three phases of testing. In the first phase, a first address in the memory is initialized by writing an initial set of data to the address. Then data is read from the address just written to and this data is modified to produce a set of modified data. The modified data is then written to another address in the memory. The steps of reading, modifying, and writing modified data back to the memory are repeated until all addresses in the memory have been written to. Thereafter, the data values stored in the memory are compared to a reference list of data values to determine whether the memory contains a defect. In phase two, the steps of phase one are repeated except that the first address in the memory is initialized by writing a set of data which is the complement of the initial set of data used in phase one. Phase two, in effect, complements the contents of each address in the memory to ensure that each cell in the memory is written with both a 0 and a 1.

Abstract: A method and system are disclosed wherein error detection codes are used for detecting and handling hardware errors in a memory table. Before each address and associated data are entered into the memory table, an error detection code is generated for both the address and the data. The address, data, and corresponding error codes are stored in the same entry line in the memory table. When the table receives an input address from a CPU, the input address is compared to all of the addresses stored within the memory table. If any stored address matches the input address, the matched address is outputted along with its associated data and its corresponding error codes. The matched address and its associated data are each processed with its corresponding error code to determine whether the outputted address and data are identical to the address and data used to generate the error codes.

Abstract: A circuit and method for detecting multiple matches or hits in a content addressable memory (CAM) are disclosed. The circuit includes a logarithmic index generator or encoder, and a converter which provides a unary signal to an attached random access memory (RAM) in order to protect the RAM from simultaneous multiple addressing attempts. The circuit also includes a plurality of inverters for inverting the unary signal, and generates a signal indicating the presence of multiple matches in the content addressable memory when corresponding digits of the inverted unary signal and an address signal are both asserted. The circuitry for generating the multiple match signal includes a plurality of AND gates coupled to output lines of the CAM, a plurality of line transistors, and a pull-up transistor coupled to a multiple match or hit line.

Abstract: A multiplier tree sums the partial products of a multiplication operation, employing a regular hierarchical arrangement of bit adders that accept nine initial inputs and a carry input and produce three outputs and a carry output. The regularity of the structure of the bit adder allows it be used to form an array of bit adders to sum twenty-seven input bits and ten carry input bits to produce three output bits and ten carry outputs bits. These bit adders form the basis of the multiplier tree. The multiplier tree using this structure can sum the partial products from a 52 to 54 bit multiply operation in no more adder delays than a Wallace tree, but with a more regular structure. A method for reducing nine input signals to three output signals segregates the input signals into sets of signals and combines them into reduced sets of logically equivalent signals.

Abstract: A structure of logic gates, partial product circuits, and a multiplier tree is described for multiplying of two operands which may contain denormalized numbers in the same amount of time as needed to multiply normalized numbers. The generation of the most significant bits ("hidden bits") of the significands of the operands from the operand exponents, and the production of the partial products that are dependent on these hidden bits, is accomplished in parallel with the generation of the partial products of the expressed bits of the significands of the operands and the first level of the multiplier tree. The fraction field partial products are input into the top level of a multiplier tree comprised of various order adders and wires. The hidden bit partial products are then input into the body of the multiplier tree instead of the top level. Additional adders are allocated to accommodate these additional inputs, but without lengthening the longest serial path from the top to the bottom of the multiplier tree.

Abstract: Apparatus and methods for early quotient completion in arithmetic division include a quotient digit generator, one or more asynchronous shift registers and a remainder comparison block. As quotient digits are generated, each digit is transferred to a different asynchronous shift register in turn. Digits are immediately propagated down each shift register to the next most significant digit position. During propagation digits are also repeated at all lesser significant digit positions. At the end of a digit generation cycle, when all asynchronous shift registers have received one new digit, the remainder comparison block determines if the current remainder is the same as the last period's remainder. If not, the remainder comparison block sends a reset signal to all the shift registers, sending reset spacers along each register that reset all duplicate versions of the last digits sent. The registers are then ready to receive next period's series of quotient digits.

Abstract: A content addressable memory cell is able to store a state representing "Don't Care", by storing two bits of data. The "Don't Care" state is indicated by storing two identical bits corresponding to a predetermined value, so that the cell indicates a match regardless of the match data. When the cell is not in the "Don't Care" state, two complementary bits are stored, so that the cell indicates a match only when the match data matches the state of the first of the two bits.

Abstract: A CMOS tri-state buffer circuit transfers digital signals between a first digital circuit system operating at 3.3 Volts and a second system operating at 5 Volts. The buffer circuit receives an active high enable signal and a data signal as inputs to a tri-state select network. When the enable signal is high, data is propagated through a driver stage and onto a data bus in the second system. Driver clamp circuitry and an n-well voltage controller operate conjunction with the driver stage to prevent the 5 volt supply of the second system from interfering with the circuitry of the of the 3.3 Volt system. A clamped line driver transmits signals from the 5 Volt system to the 3.3 Volt system.

Abstract: CMOS domino logic is normally used only in two phases: precharge and logic evaluation. The invention uses a third phase to store data, which allows domino logic gates to be cascaded and pipelined without intervening latches. The inputs to this system must have strictly monotonic transitions during the logic evaluation phase and the precharge signal must be active during only the precharge phase. Furthermore, the pipelined system can feed its output back to the input to form an iterative structure. Such a feedback pipeline is viewed as a "loop" or "ring" of logic which circulates data until the entire computation is complete.