Workstation housing
Latest HaL Computer Systems, Inc. Patents:
- Processor structure and method for tracking instruction status to maintain precise state
- Method and apparatus for coordinating the use of physical registers in a microprocessor
- Apparatus and method for controlling instruction flow by using a matrix of transmission gates in super-scaler microprocessor and selectively delaying microprocessor instruction execution based on resource availability
- Merging data using a merge code from a look-up table and performing ECC generation on the merged data
- Lookaside buffer for inputting multiple address translations in a computer system
Description
FIG. 1 is a front perspective view of the workstation housing;
FIG. 2 is a rear perspective view of the workstation housing;
FIG. 3 is a top plan view of the workstation housing;
FIG. 4 is a front plan view of the workstation housing;
FIG. 5 is a rear plan view of the workstation housing;
FIG. 6 is a side plan view of the workstation housing; and,
FIG. 7 is a bottom plan view of the workstation housing.
FIGS. 1, 2, and 6 are drawn on a reduced scale.
Referenced Cited
Patent History
Patent number: D361321
Type: Grant
Filed: Nov 29, 1993
Date of Patent: Aug 15, 1995
Assignee: HaL Computer Systems, Inc. (Campbell, CA)
Inventors: Fred J. Berkowitz (Los Gatos, CA), Thomas D. Carroll (San Jose, CA), Eric M. Monsef (San Jose, CA), Robert A. Musetti (Cupertino, CA)
Primary Examiner: Freda S. Nunn
Attorney: Albert C. Smith
Application Number: 0/15,786
Type: Grant
Filed: Nov 29, 1993
Date of Patent: Aug 15, 1995
Assignee: HaL Computer Systems, Inc. (Campbell, CA)
Inventors: Fred J. Berkowitz (Los Gatos, CA), Thomas D. Carroll (San Jose, CA), Eric M. Monsef (San Jose, CA), Robert A. Musetti (Cupertino, CA)
Primary Examiner: Freda S. Nunn
Attorney: Albert C. Smith
Application Number: 0/15,786
Classifications
Current U.S. Class:
D14/102