Abstract: A shift register unit, a driving method thereof, a gate driver and a display device are provided. The shift register unit includes a first input circuit, an output circuit and a charging enhancement circuit. The first input circuit is configured to charge a first node in response to a first input signal; the output circuit is configured to output, under control of a level of the first node, a shift signal for a row-by-row shift of scanning and a first output signal for driving one row of sub-pixel units in a display panel to perform display scanning; and the charging enhancement circuit is configured to further enhance the level, of the first node in response to a charging enhancement signal. The shift register unit may enhance the level of the first node and the reliability of the gate driver and the display device consisted of the shift register unit.

Abstract: The present disclosure provides a shift register unit, a gate driving circuit and compensation method and driving method thereof, and a display device. The shift register unit includes: a shift register circuit having a detection node, the shift register circuit is configured to receive an input signal and a clock signal, and generate an output signal based on the clock signal under control of the input signal; and a detection circuit coupled to the detection node of the shift register circuit, the detection circuit is configured to generate a detection signal based on a potential of the detection node.

Abstract: A display substrate including a plurality of light emitting elements respectively in a plurality of subpixels configured to emit light for image display is provided. A respective one of the plurality of subpixels includes a base substrate; a first auxiliary cathode; a passivation layer; a first insulating layer; a second auxiliary cathode; a second insulating layer; and a pixel definition layer. The display substrate has a cathode aperture extending through the pixel definition layer and an auxiliary cathode aperture extending through the first insulating layer and the passivation layer. A cathode of a respective one of the plurality of light emitting elements extends into the cathode aperture to electrically connect with the second auxiliary cathode. The second auxiliary cathode extends into the auxiliary cathode aperture to electrically connect with the first auxiliary cathode.

Abstract: A shift register unit includes a first node connection branch, an ON/OFF control circuit and a third node control circuit. A first end of the first node connection branch is electrically connected to first node, and a second end of the first node connection branch is electrically connected to a third node. The first node connection branch is configured to control the first node to be electrically connected to the third node under the control of a potential at the first node. The ON/OFF control circuit is configured to control the third node to be electrically connected to a first voltage end under the control of the potential at the first node. The third node control circuit is configured to reset a potential at the third node under the control of a resetting signal from a resetting end and a potential at a second node.

Abstract: An array substrate includes an array of a plurality of subpixels including a plurality of columns of subpixels respectively spaced apart by a plurality of inter-subpixel regions; a plurality of pixel driving circuits respectively driving light emission of the plurality of subpixels; and a plurality of detection and compensation lead lines respectively configured to respectively detect signals in the plurality of subpixels and respectively compensate signals in the plurality of subpixels. A respective one of a plurality of detection and compensation lead lines is disposed in a first inter-subpixel region between two directly adjacent columns of subpixels. The respective one of the plurality of detection and compensation lead lines is spaced apart by at least one columns of subpixels from a signal line configured to transmit an alternating current and arranged along a direction parallel to the respective one of the plurality of detection and compensation lead lines.

Abstract: A display panel includes a plurality of pixel driving circuits and a plurality of sense lines. The pixel driving circuits are capable of being divided into a plurality of rows of pixel driving circuits each arranged in a first direction and divided into a plurality of columns of pixel driving circuit each arranged in a second direction intersected with the first direction. Each pixel driving circuit includes a detection transistor. The sense lines are arranged at intervals and extending along the second direction, and are configured to provide reference voltage signals to the plurality of pixel driving circuits. Each detection transistor is electrically connected to one of the plurality of sense lines, and in pixel driving circuits in a same column, detection transistors in any two adjacent rows are electrically connected to different sense lines.

Abstract: A shift register unit includes a pull-down sustaining sub-circuit and a pull-down sub-circuit. The pull-down sustaining sub-circuit includes: a first transistor having a control electrode configured to input a pull-down sustaining signal, a first electrode connected to a first power signal terminal, and a second electrode connected to a pull-down node; a first capacitor; and a second transistor having a control electrode connected to an input signal terminal. The pull-down sub-circuit includes: a third transistor having a control electrode connected to the first terminal of the first capacitor, a first electrode connected to a pull-up node, and a second electrode connected to the second power signal terminal; a fourth transistor having a control electrode connected to the first terminal of the first capacitor, a first electrode connected to an output sub-circuit, and a second electrode connected to the second power signal terminal.

Abstract: The present disclosure provides a shift register unit and a method for driving the same, a gate driving circuit and a method for driving the same, and a display apparatus. The shift register unit includes a first input sub-circuit to an Nth input sub-circuit and a first output sub-circuit to an Nth output sub-circuit. N is an integer greater than or equal to 2. For n=1, 2, . . . , N, an nth input sub-circuit is electrically coupled to an nth input signal terminal, a first level signal terminal and a pull-up node, and an nth output sub-circuit is electrically coupled to an nth clock signal terminal, the pull-up node and an nth output signal terminal.

Abstract: A shift register unit, a gate drive circuit, a display panel, a display device and a driving method. The shift register unit includes a first input circuit, a second input circuit, a first output circuit, a second output circuit, a first reset circuit and a second reset circuit. The first input circuit is configured to control a level of a first node in response to a first input signal. The second input circuit is configured to control the level of the first node in response to a second input signal. The first output circuit is configured to output a first clock signal to a first output terminal under a control of the level of the first node. The second output circuit is configured to output a second clock signal to a second output terminal under the control of the level of the first node.

Abstract: A shift register unit, a gate driving circuit, a display device, and a method for controlling a shift register unit are provided. The shift register unit includes a first input sub-circuit, a second input sub-circuit, a first isolation sub-circuit, and a first output sub-circuit. The first input sub-circuit is configured to control a potential of a first node. The second input sub-circuit is configured to control a potential of a second node. The first isolation sub-circuit is configured to control conduction and interruption of electrical coupling between the first node and the second node. The first output sub-circuit is configured to output a gate driving signal in a display phase and output a compensation driving signal in a field blanking phase.

Abstract: Embodiments of the present disclosure provide a method of manufacturing a display substrate. The method includes: forming a first electrode layer on a substrate, the first electrode layer including a plurality of first electrodes arranged in an array; performing a surface treatment on the plurality of first electrodes, such that an affinity of a surface of each of the plurality of first electrodes gradually increases from a central portion of the surface to a peripheral portion of the surface around the central portion, or the affinity of the central portion of the surface is less than the affinity of the peripheral portion of the surface; and forming a light emitting functional layer on the surfaces of the plurality of first electrodes subjected to the surface treatment. Embodiments of the present disclosure further provide a display substrate, a display panel, and a mask.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first sub-circuit, a second sub-circuit, and a leakage prevention circuit. The first sub-circuit comprises a first input circuit and a first output circuit, the first input circuit is configured to control a level of a first node in response to a first input signal. The second sub-circuit comprises a second input circuit and the second output circuit. The leakage prevention circuit is connected to the first node, and is configured to control a level of the leakage prevention node under control of the level of the first node, so that a circuit connected between the first node and the leakage prevention node is turned off, and a circuit connected between the second node and the leakage prevention node is turned off.

Abstract: The present application discloses a shift-register unit. The shift-register unit includes a first sub-unit including a first input circuit coupled via a first node to a first output circuit. The first input circuit is configured to control a voltage level of the first node in response to a first input signal and the first output circuit is configured to output a shift-register signal and a first output signal in response to the voltage level of the first node. Additionally, the shift-register unit includes a second sub-unit including a second input circuit coupled via a second node to a second output circuit. The second input circuit is configured to control a voltage level of the second node in response to the first input signal and the second output circuit is configured to output a second output signal in response to the voltage level of the second node.

Abstract: A shift register unit, a driving method thereof, a gate driver and a display device are provided. The shift register unit includes a first input circuit, an output circuit and a charging enhancement circuit. The first input circuit is configured to charge a first node in response to a first input signal; the output circuit is configured to output, under control of a level of the first node, a shift signal for a row-by-row shift of scanning and a first output signal for driving one row of sub-pixel units in a display panel to perform display scanning; and the charging enhancement circuit is configured to further enhance the level of the first node in response to a charging enhancement signal. The shift register unit may enhance the level of the first node and the reliability of the gate driver and the display device consisted of the shift register unit.

Abstract: The present disclosure provides a gate driving unit and method, a gate driving module and circuit, and a display device. The gate driving unit includes: an external compensation control signal output terminal, a gate driving signal output terminal, an external compensation control signal output circuit, a gate driving signal output circuit, a pull-up control circuit and a pull-down node control circuit.

Abstract: The present disclosure provides an organic light emitting diode (OLED) display device and control method thereof. The OLED display device includes: a plurality of subpixels that are arranged in an array having a plurality of rows and a plurality of columns, wherein at least one of the subpixels comprises a control transistor, a light emitting element, and a drive transistor for driving the light emitting element; a plurality of detection lines, wherein at least one of the detection lines is electrically connected with the control transistors of subpixels in a same column, for detecting an electrical property of the drive transistors of subpixels in the same column through respective control transistors; and a plurality of group detection control lines, wherein at least one of the group detection control lines is electrically connected with control transistors of a subpixel group, the subpixel group comprising subpixels in a first row and subpixels in a second row.

Abstract: Disclosed is a display substrate and a display apparatus, the display substrate includes a display area and a peripheral area, wherein the display substrate includes M groups of shift registers and N groups of clock signal lines in the peripheral area, M is greater than or equal to N, M and N are positive integers, each group of shift registers is connected with a group of gate lines positioned in the display area, and adjacent N groups of shift registers are connected with N groups of clock signal lines one by one correspondingly. The N groups of clock signal lines are disposed side by side along a first direction, and configured to make, through an adjustment of a wiring sequence, an impedance difference between two groups of clock signal lines connected to any two adjacent groups of shift registers be less than or equal to an impedance threshold value.

Abstract: The present disclosure provides a display panel, a method thereof and a display device. The display panel includes a gate line group, a gate driving circuit, and a sub-pixel unit group. The sub-pixel unit group includes N rows of sub-pixel units, the gate line group includes (N+1) gate lines. The sub-pixel unit includes a light emitting unit, a pixel driving circuit, and a sensing circuit. The gate driving circuit includes output terminals, and is configured to sequentially output gate scanning signals through the output terminals. Each gate line is coupled to one corresponding output terminal. In the sub-pixel unit group, the pixel driving circuit in a sub-pixel unit in an n-th row is coupled to an n-th gate line; and the sensing circuit in the sub-pixel unit in the n-th row is coupled to a (n+1)-th gate line, where 1?n?N, and n is an integer.

Abstract: The present disclosure provides a shift resister unit, a gate driving circuit, a display device, and a method for controlling a shift register unit. The shift register unit incudes a first input sub-circuit, a first output sub-circuit, a first reset sub-circuit, a second input sub-circuit, and a third input sub-circuit. The first input sub-circuit is configured to change a potential of a first node in a first phase. The first output sub-circuit is configured to output a gate driving signal in the first phase and output a compensation driving signal in a second phase. The first reset sub-circuit is configured to reset the first node. The second input sub-circuit is configured to change a potential of a second node in the first phase and maintain the potential of the second node. The third input sub-circuit is configured to change the potential of the first node in the second phase.

Abstract: A shift register unit, a gate driving circuit, a display device and a driving method are provided. The shift register unit includes a first input circuit, an output circuit, a first control circuit, a first reset circuit, a second input circuit, a transmission circuit, and a storage circuit. The first input circuit is configured to control a level of a first node, the output circuit is configured to provide an output signal at an output terminal, the first control circuit is configured to control a level of a second node under control of the level of the first node, the first reset circuit is configured to reset the first node and the output terminal under control of the level of the second node, and the storage circuit is electrically connected to the second node, and is configured to stabilize the level of the second node.