Abstract: A display module includes a display panel, a power supply driver, a voltage signal line, a sampling resistor and a detection and control circuit. The voltage signal line is connected between the display panel and the power supply driver. The sampling resistor is connected in series with the voltage signal line. The detection and control circuit is connected to two ends of the sampling resistor and the power supply driver. The detection and control circuit is configured to: detect a voltage across the sampling resistor or a current flowing through the sampling resistor; and control the power supply driver to generate a driving voltage equal to a preset value lower than a voltage threshold, if determining that the voltage across the sampling resistor is greater than or equal to the voltage threshold, or if determining that the current is greater than or equal to a current threshold.

Abstract: A shift register and a method of driving the same, a gate driving circuit, and a display panel are disclosed. The shift register includes a display control circuit coupled to a pull-up node, a first power supply and a first control terminal respectively; a cascade output circuit coupled to a second clock terminal, the pull-up node and a cascade output terminal; a sensing control circuit coupled to the pull-up node, the cascade output terminal, a second control terminal and a third control terminal respectively; and a signal output circuit coupled to the pull-up node, a first clock terminal and a signal output terminal.

Abstract: An array substrate includes an array of a plurality of subpixels including a plurality of columns of subpixels respectively spaced apart by a plurality of inter-subpixel regions; a plurality of pixel driving circuits respectively driving light emission of the plurality of subpixels; and a plurality of detection and compensation lead lines respectively configured to respectively detect signals in the plurality of subpixels and respectively compensate signals in the plurality of subpixels. A respective one of a plurality of detection and compensation lead lines is disposed in a first inter-subpixel region between two directly adjacent columns of subpixels. The respective one of the plurality of detection and compensation lead lines is spaced apart by at least one columns of subpixels from a signal line configured to transmit an alternating current and arranged along a direction parallel to the respective one of the plurality of detection and compensation lead lines.

Abstract: A display panel and a display device are disclosed. The display panel includes a plurality of sub-pixel units arranged in an array which includes N rows and 4M columns, sub-pixel units in each row is divided into a plurality of sub-pixel unit groups, and each sub-pixel unit group includes a first sub-pixel unit, a second sub-pixel unit, a third sub-pixel unit and a fourth sub-pixel unit which are sequentially in four adjacent columns along a first direction.

Abstract: Provided are a display substrate and a preparation method therefor, and a display apparatus, which can not only avoid jumpers generated when a light-emitting device in a sub-pixel is electrically connected to a storage capacitor, in order to avoid the risk of crosstalk, but can also increase the pixel aperture ratio of the display substrate and increase the capacitance of the storage capacitor in a pixel driving circuit.

Abstract: A display substrate, an ink-jet printing method thereof and a display apparatus are provided. The display substrate includes a base substrate. A plurality of pixel definition layers is disposed on the base substrate, and a sub-pixel region is formed between pixel definition layers. A pixel definition layer includes a first definition layer disposed on the base substrate, and the first definition layer adopts a hydrophilic material. The first definition layer includes an expansion layer capable of changing the thickness of the first definition layer.

Abstract: A shift-register unit includes a first circuit including a first input circuit coupled via a first node to a first output circuit, and a second circuit including a second input circuit coupled via a second node to a second output circuit. The first input circuit is configured to control a voltage level of the first node in response to a first input signal. The first output circuit is configured to output a shift-register signal and a first output signal in response to the voltage level of the first node. The second input circuit is configured to control a voltage level of the second node in response to the first input signal. The second output circuit is configured to output a second output signal in response to the voltage level of the second node. The first input circuit and the second input circuit have a same circuit structure.

Abstract: A shift register includes a first reset circuit having a first transistor and a second transistor, and a selection control circuit connected to a pull-down node, and control electrodes of the first and second transistors. First electrodes of the first and second transistors are connected to a first voltage terminal, and second electrodes of the first and second transistors are connected to a signal output terminal. The selection control circuit is configured to: control a line between the pull-down node and the control electrode of the first transistor, and a line between the pull-down node and the control electrode of the second transistor to be alternately closed. The first reset circuit is configured to output a voltage of the first voltage terminal to the signal output terminal under control of a potential at the pull-down node transmitted by the selection control circuit.

Abstract: Provided are a shift register unit circuit and drive method, and a gate driver and a display device. The shift register unit circuit includes a first sub-unit circuit, a second sub-unit circuit, a third sub-unit circuit, and a fourth sub-unit circuit. Responsive to providing a corresponding input pulse and clock signal, the shift register unit circuit is configured output first, second, third, and fourth output signals. The shift register unit circuit is configured such that a fifth node is in conduction with a second node at least while the reset pulse is active.

Abstract: The present application discloses a shift-register unit. The shift-register unit includes a first sub-unit including a first input circuit coupled via a first node to a first output circuit. The first input circuit is configured to control a voltage level of the first node in response to a first input signal and the first output circuit is configured to output a shift-register signal and a first output signal in response to the voltage level of the first node. Additionally, the shift-register unit includes a second sub-unit including a second input circuit coupled via a second node to a second output circuit. The second input circuit is configured to control a voltage level of the second node in response to the first input signal and the second output circuit is configured to output a second output signal in response to the voltage level of the second node.

Abstract: A shift register includes an output sub-circuit, a cascade sub-circuit and at least one additional output sub-circuit. The output sub-circuit is configured to transmit a first clock signal received at the first clock signal terminal to the output signal terminal under control of a potential at the pull-up node, so as to scan a gate line coupled to the output signal terminal. The cascade sub-circuit is configured to transmit a second clock signal received at the second clock signal terminal to the cascade node under the control of the potential at the pull-up node. Each additional output sub-circuit is configured to transmit a clock signal received at a corresponding clock signal terminal to a corresponding additional output signal terminal under control of a potential at the cascade node, so as to scan a gate line coupled to the corresponding additional output signal terminal.

Abstract: The present disclosure provides a shift register unit, a gate driving circuitry and a method for driving the gate driving circuitry. The shift register unit includes an input circuitry, a first latch circuitry, a second latch circuitry and an output end. The input circuitry is configured to output an input control signal to the first latch circuitry in accordance with a first level signal, a second level signal and a first ON signal. The first latch circuitry is configured to output an output signal as a gate driving signal via the output end in accordance with a first clock signal and the input control signal, and latch the output signal. The second latch circuitry is configured to output a second ON signal in accordance with a second clock signal and the output signal, and latch the second ON signal.

Abstract: Provided are a shift register unit and a control method thereof, a gate driving circuit and a control method thereof, and a display apparatus. The shift register unit may include: a first shift register coupled to an input signal terminal, a first clock signal terminal and a second clock signal terminal. The first shift register is configured to generate a first output signal based on the signal at the first clock signal terminal and generate a second output signal based on the signal at the second clock signal terminal; and a second shift register coupled to the input signal terminal and a third clock signal terminal, the second shift register is configured to generate a third output signal based on the signal at the third clock signal terminal; and a pull-up node of the first shift register is coupled to a pull-up node of the second shift register.

Abstract: A shift register unit and a method for driving the same, and a gate driving circuit are provided. The shift register unit includes: an adjustment circuit coupled between an input signal terminal and an input node of the shift register unit, and configured to couple or decouple the input signal terminal and the input node under control of a potential at the input signal terminal; an input circuit for providing a potential at the input node to the pull-up node under control of a potential at the input signal terminal; an output circuit for receiving a clock signal from the clock signal terminal and provide an output signal to the output signal terminal based on the received clock signal under control of a potential at the pull-up node; and a control circuit for controlling a potential at the output signal terminal under control of a potential at the pull-up node.

Abstract: The present disclosure relates to a method for manufacturing an OLED light emitting device, an OLED light emitting device, and an OLED display device. The method for manufacturing an OLED light emitting device according to an embodiment of the present disclosure includes forming a pixel defining layer on a substrate, wherein the pixel defining layer comprises a lyophilic material or a lyophobic material and the pixel defining layer comprises a plurality of openings which are spaced apart from each other; forming an anode layer on the substrate and in each opening; adding a preset solvent having a property opposite to that of the lyophilic material or the lyophobic material of the pixel defining layer in an OLED film layer ink; and ink-jet printing the OLED film layer ink on the anode layer and in each opening to form an OLED film layer.

Abstract: An array substrate and a display device are provided. The array substrate includes at least one data line and a plurality of sub-pixel groups arranged in an array along a first direction and a second direction. At least one sub-pixel group includes two rows of sub-pixels, one row of the two rows of sub-pixels includes a first color sub-pixel and a second color sub-pixel, and the other row of the two rows of sub-pixels includes a third color sub-pixel; the first color sub-pixel, the second color sub-pixel and the third color sub-pixel in each sub-pixel group are connected to a same data line of the at least one data line.

Abstract: The present disclosure relates to the field of display technology, and provides a shift register unit and a driving method thereof, a gate driving circuit, and a display panel. The shift register unit includes: an input circuit, a charging circuit, an inverter circuit, an output circuit, and a pull-down circuit. The input circuit is connected to a second clock signal terminal, a signal input terminal and a first node. The inverter circuit is connected to the signal input terminal, the second clock signal terminal, a first power supply terminal, a second power supply terminal and a pull-down node. The output circuit is connected to the pull-up node, the first power supply terminal and an output terminal. The pull-down circuit is connected to the pull-down node, the second power supply terminal, the pull-up node, and the output terminal.

Abstract: Pixel driving method for driving pixel unit, display driving method and display substrate are provided. The pixel unit includes pixel driving circuit, including driving transistor, storage capacitor, and data writing circuit, the driving transistor has control electrode coupled to first terminal of the data writing circuit and the storage capacitor, and first electrode coupled to second terminal of the storage capacitor, and second terminal of the data writing circuit is coupled to data line. The pixel driving method includes: loading a data voltage into the data line, and controlling the first and second terminals of the data writing circuit to be connected; controlling the data line to be floating, and maintaining connection between the first and second terminals of the data writing circuit to reduce gate-source voltage of the driving transistor; and controlling the first and second terminals of the data writing circuit to be disconnected.

Abstract: A pixel circuit and a driving method thereof, and a display device, the pixel circuit being configured to drive a light-emitting element and including: a node control sub-circuit, which is configured to provide a first node with a signal of a data signal end and provide a second node with a signal of a control signal end under the control of a first scanning end; a driving sub-circuit, which is configured to provide the second node with a driving current under the control of the first node and the second node; a storage sub-circuit, which is configured to store electric charge between the first node and the second node; a reading sub-circuit, and the light-emitting element, which is electrically connected to the second node and a second power supply end, respectively.

Abstract: Shift register includes signal writing circuit, voltage control circuit and output circuit. The signal writing circuit is configured to write inverted signal of input signal provided by signal input terminal into second node responsive to control of second clock signal provided by second clock signal terminal. The voltage control circuit is configured to write first operating voltage into first node and write second clock signal into third node in voltage control circuit in response to control of voltage at first node, write second operating voltage into third node in response to control of second clock signal and write first clock signal provided by first clock signal terminal into first node in response to control of voltage at third node and first clock signal. The output circuit is configured to write second or first operating voltage into signal output terminal in response to control of voltage at first or second node.