Abstract: A method and apparatus for generating an AC voltage with user defined inductance and resistance values in series therewith is described. The output voltage of the AC source is sampled and a signal indicative of the total current being generated is derived. The signal is scaled to model a series resistance and scaled and differentiated to model a series inductance. The modelled series resistance and inductance are then combined with the output voltage. Different inductances and resistances can be modelled merely by changing the user's input to the microcontroller that controls the operation of the present invention.

Abstract: High speed power supply transients are suppressed in a system having fast edges and where a radial transmission line exists between the power supply and ground planes, by terminating the edges of the PCB in it characteristic impedance. In practice, this means approximating a continuous construct with many spaced instances of a discrete resistance. The dissipative terminations themselves are resistive, and if placed directly between the power supply and ground would needlessly dissipate a great deal of DC power. To prevent that they are AC coupled with a high quality coupling capacitor of sufficient capacitance to allow the resulting impedance to appear predominately resistive at and above the lowest frequency of interest, say, 100 MHz. Because of the confused nature of the reflection that may be generated at arbitrary locations within the interior of the PCB, there may well be "hot spots" within that interior that would benefit from the placement of a selected AC coupled load at or near such a spot.

Abstract: An n-around nuller in a disk drive track-follow loop servo system is optimized by maximizing its feedforward orthogonality (channel separation). Sine and cosine terms (signals) are injected into the track-follow loop, thereby creating the separate channels (signals), to reduce the amplitude of the n-around component. The Fourier sum is then taken in connection with a phase delay variable and integrated to produce the proper feedback for maximizing orthogonality and minimizing instability. Specifically, the feedforward cosine term is low-pass filtered to find its average value. A step is then fed into the feedforward sine term and the response of feedforward cosine is observed. Feedforward cosine is then integrated to evaluate how much "cross talk" there is between the two channels. Once the integral sum is found, it is used as a feedback element for tuning the sine and cosine terms injected into the channels, thereby maximizing feedforward orthogonality and minimizing servo system nuller instability.

Abstract: Arrays of vertical cavity surface emitting lasers ("VCSEL"s) used for illumination in both infra-red and visible light wavelengths are described. By using several different arrays, each array generating light of a different wavelength, a replacement for conventional lighting sources can be obtained. The present invention offers lower power consumption and longer operating lifetime than known lighting technologies.

Abstract: An apparatus and method are disclosed for improving the stability of the frequency of vibration of an oscillator signal produced by an oscillator circuit. In a preferred embodiment of the present invention, a quartz crystal resonator is one arm of a bridge which generates a bridge signal which varies in accordance with the vibrating frequency of the resonator. A synchronous demodulator responds to the bridge signal for producing an error signal which is converted into a control signal. A control circuit receives the control signal and changes its reactance when the resonator is no longer vibrating at its unperturbed resonance frequency so that the vibration frequency of the resonator connected to the control circuit is returned to its resonant frequency. An automatic level control circuit is also included for controlling the drive level of the signal exciting the resonator.

Abstract: A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with the data bus at a second clock frequency. The system includes a clock generator for generating a bus clock signal at the first clock frequency and a chip clock signal at the second clock frequency wherein the first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein the bus and chip clock signals are synchronized once every N cycles of the chip clock signal. The clock generator also generates a synchronization signal indicating the chip clock signal cycle in which the bus and chip clock signals are synchronized. The circuit block includes an interface circuit for receiving and transmitting data on the bus.

Abstract: A method for reducing the volume of ink applied to high-density print regions by depleting certain pixels in these regions avoids problems associated with excessive ink, improves economy, and yet retains print quality. Pixels located along the edges of high-density regions are identified and not depleted, thus preserving the sharp image demarcations characteristic of high quality printing. An upper bound for the percentage of depleted pixels may be chosen. A two-dimensional depletion table having certain entries designated as potential depletion candidates is tiled across a pixel image to be depleted. The designated entries are spaced apart within the table. If a pixel in the image is a candidate to be depleted according to the depletion table and if it is not an edge pixel, then it is depleted.

Abstract: A circuit and method for iterative generation of the variables used in vector generation and linear interpolation. Most significant bits are added in a last pipeline stage. Less significant bits are added in earlier pipeline stages. Breaking addition into multiple parts with each part having fewer bits to add enables a faster iterative cycle rate compared to a single long adder. Part of the vector generation algorithm requires a decision step based on the sign of the complete addition. Since this sign is generated in the last stage of the pipeline, it is not available at the time needed by earlier stages of the pipeline. Therefore, all possible combinations of outcomes for earlier pipeline stages are simultaneously speculatively computed for use by following pipeline stages.

Abstract: A system of encoding a plurality of logic paths. A number of logic paths are subdivided into groups of N, N being greater than one. Each group of N logic paths is encoded such that an assertion of a given combination of the N logic paths results in a predetermined one out of 2.sup.N signal lines being asserted. Simultaneous assertion of more than one of the 2.sup.N signal lines is defined as an invalid state. A simultaneous non-assertion of all of the 2.sup.N signal lines enables precharging of the signal lines for dynamic operation. 1-of-2.sup.N encoding enables transmission of N variables by firing one out of N wires (rather than every wire, as in static logic, or one out of two wires, as in mousetrap logic). Signal degradation due to noise and coupling is reduced. In a multiplexer, 1-of-2.sup.N encoding reduces the load on the multiplexer's shift lines. Several 1-of-2.sup.

Abstract: A zymbolic history management system (ZHMS) allows a user to create annotated symbolic links (zymlinks) to files in a shared file system. A single link is created to each file of the shared file system which a user wishes to access. A zymlink to the shared file system may be updated via a zupdate command. Rather than selectively updateing individual files, a user simply zupdate's whole trees of files. When it comes time to edit files, a user makes use of standard history managed file system commands to obtain a writable copy of a file. Use of one of these commands destroys a zymlink corresponding to the file, and substitutes a privately owned copy of the file on a user's disk. When the edited file is checked back into the history managed file system, a read-only copy of the file remains on a user's disk. When a user updates his or her file system, the read-only file copy may be replaced with a new zymlink. A user will normally view current versions of shared files.

Abstract: A wet wiping system is provided that is particularly useful for wiping an inkjet printhead that uses pigment based ink. A wet wiping method comprises an admitting step, where ink is admitted though printhead nozzles, either by firing the inkjet cartridge with a low thermal turn on energy, or through capillary action provided by placing the printhead in contact with a wicking pad. In a dissolving step, any accumulated ink residue adjacent the nozzles is dissolved with the admitted ink. In a wiping step, the admitted ink and any dissolved ink residue is wiped from the printhead. One wet wiper has a cellulose acetate polyester blade supported on at least one side by a foam block. The wicking pad may have a ramped portion for gradually contacting the printhead, or a domed wicking surface that is compressed upon contact with the printhead to facilitate the capillary action.

Abstract: The contact pads of a print cartridge are formed on a flexible tape. Each of the uniformly spaced contact pads is preferably a square separated from an adjacent square by a minimum distance to provide each contact pad with a maximum area. The contact pads are arranged on the flexible tape only along the side portions of the plastic print cartridge body, where body is generally flat, to avoid the pads being located in the sunken middle portion of the body, where the sinking occurs during the injection molding process used to form the body. This improves the reliability of the interconnection between the pads and the printer electrodes.

Abstract: A host computer includes a processor, a first memory for storing a bit map representation of an image to be printed, and a second memory for storing a control language representation of an image to be printed. The host computer further includes a printer driver for enabling dispatch of the bit map representation to a connected printer. The printer includes a print engine, a printer processor and control memory for storing bit map control code which controls the printer processor to render the print engine able to print an image defined by a bit map representation. The control memory further includes control language code for controlling the printer's processor to render the print engine able to print an image defined by a control language representation. Within the host computer is an interface module, controlled by the host printer driver, for interrogating status information from the printer.

Abstract: An integrated liquid sample handling system for matrix-assisted laser-desorption/ionization time-of-flight mass spectroscopy (MALDI-TF MS) is described. The integrated system comprises a miniaturized sample handling compartment containing a MALDI ionization surface for separating, chemically manipulating and detecting analytes by MALDI -TOF MS. The miniaturized integrated sample handling system disclosed herein is applicable to a wide range of analytical problems that require separation and/or chemical manipulation of a sample prior to mass analysis as part of the analytical procedure.

Abstract: An ultrasonic probe for imaging tissues from inside a patient's body cavity is disclosed. The ultrasonic probe includes an end portion having a back and forth pivotable transducer assembly for transmitting an ultrasonic beam. The transducer assembly is supported by a silicon-containing support about a cavity and includes a transducer block on a base layer connected to the support via one or more twistable or flexible support arms. The transducer block includes a backing layer, a transducer layer on said backing layer, and an acoustic matching layer on the transducer layer. A bottom electrode in the transducer block penetrates the backing layer to connect electrically to a bottom face of the transducer layer to a conductor which is on a first face of the block. A top electrode penetrates the acoustic matching layer to connect electrically to a top face of the transducer layer to a conductor on a second face of the block for activating the transducer layer.

Abstract: A compiler that facilitates efficient insertion of explicit data prefetch instructions into loop structures within applications uses simple address expression analysis to determine data prefetching requirements. Analysis and explicit data cache prefetch instruction insertion are performed by the compiler in a machine-instruction level optimizer to provide access to more accurate expected loop iteration latency information. Such prefetch instruction insertion strategy tolerates worst-case alignment of user data structures relative to data cache lines. Execution profiles from previous runs of an application are exploited in the insertion of prefetch instructions into loops with internal control flow. Cache line reuse patterns across loop iterations are recognized to eliminate unnecessary prefetch instructions. The prefetch insertion algorithm is integrated with other low-level optimization phases, such as loop unrolling, register reassociation, and instruction scheduling.

Abstract: An optical disk drive system having a means for detecting off-track conditions with high reliability under conditions causing the objective lens to deviate from optimal focus, such as in the presence of external mechanical shocks. As the lens travels out of focus, the ability to resolve features decreases due to the loss of image contrast, causing a loss of tracking error signal (TES) gain. A digital signal processor (DSP) compensates for this loss by continuously determining an adjustable TES threshold representing the same desired percentage off track and same percentage of TES amplitude. A straight line approximation of this ideal adjustable threshold is used as a threshold to determine if the beam is within the desired amount off track. Alternatively, the DSP amplifies the TES by an amplification function to maintain the TES at a constant value while the objective lens travels out of focus. The TES amplification function is a straight line approximation of an ideal amplification function.

Abstract: In a computer graphics system, per vertex depth cue scale factor values and depth cue rendering parameters are determined for the vertices of a triangle to be displayed. Interpolation circuitry determines a per pixel depth cue scale factor and per pixel color values for each of the pixels in the triangle. When the computer graphics system includes texture mapping hardware, a blending circuit combines the per pixel color values and the texture mapped color values to provide per pixel resulting color values. The per pixel depth cue scale factor value, the per pixel resulting color values and a depth cue color are used to determine per pixel depth cued color values for each of the pixels in the triangle. Accurate depth cueing is achieved with or without texture mapping.