Abstract: A soft information module is coupled between one or more flash memory devices and a decoder. The soft information module receives a putative value of one or more memory cells of the one or more flash memory devices based on a read of the one or more memory cells at an initial read level, and one or more respective indicators of whether the putative value was read at one or more respective different read levels offset from the initial read level, and receives a page indicator for the read. The soft information module determines a cell program region for the read based on the putative value, the one or more respective indicators, and the page indicator, identifies a predetermined confidence value for the region, and provides the confidence value to the decoder for association with the putative value, the confidence value being representative of a likelihood that the one or more memory cells was programmed to the putative value.

Abstract: In one aspect, the present disclosure provides a storage device for accounting for transmission errors to improve a usable life span of memory blocks. In some embodiments, the storage device includes: a memory array including a plurality of memory blocks; and a memory controller in communication with the memory array via an interface, wherein the memory controller is configured to detect an error event associated with data from one of the plurality of memory blocks; determine an origin of the error event; increment an error count if the origin of the error event indicates a data error in the one of the plurality of memory blocks and not if the origin of the error event indicates a transmission error; compare the error count to a threshold value; and mark the one of the plurality of memory blocks as bad when the error count exceeds the threshold value.

Abstract: A device includes volatile memory; one or more non-volatile memory chips, each of which is for storing data moved from the volatile-memory; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from a primary power source; a controller in communication with the volatile memory and the non-volatile memory, wherein: the controller is programmed to move data from the volatile memory to the non-volatile memory chips upon a loss of power of the primary power source of the volatile memory; and the at least one parameter describing the volatile memory are stored in at least one of the non-volatile memory chips that store the data moved from the volatile memory. In some aspects the at least one parameter includes serial presence detect information.

Abstract: A method applies a first set of consecutive pulses to flash memory cells in one or more flash memory devices to program the flash memory cells using a first pulse increment, a voltage of each consecutive pulse of the first set being incremented by the first pulse increment. On receiving an indication that the flash memory cells are partially programmed after the first set of consecutive pulses is applied, the first pulse increment is adjusted to an adjusted pulse increment based on a number of program/erase cycles associated with the flash memory cells. A second set of consecutive pulses to the flash memory cells is then applied using the adjusted pulse increment, a voltage of each consecutive pulse of the second set being incremented by the adjusted pulse increment.

Abstract: A method of transferring data in a flash storage device is provided. A plurality of data segments for transfer between a memory buffer and a plurality of flash memory devices via a plurality of flash memory interfaces is associated with a plurality of respective memory commands. The plurality of memory commands are allocated among the plurality of flash memory interfaces, with each respective memory command being queued at a respective memory interface for transfer of a respective data segment associated with the respective memory command. The plurality of data segments are transferred between the memory buffer and the plurality of flash memory devices based on the plurality of memory commands, with each respective data segment being transferred via the memory interface to which the memory command associated with the respective data segment is queued. The data segments are transferred sequentially in an order corresponding to the queued memory commands.

Abstract: A method populates a parameter set for dynamically adjusting an operating condition in a memory block of a non-volatile memory circuit. A desired condition limit is identified, and a first parameter is computed as a function of a first memory operation to be performed on the memory block. The first parameter is included in a parameter set, and the memory block is cycled until the operating condition reaches the desired condition limit. After cycling, a second parameter is determined as a function of a second memory operation to be performed on the memory block, and the second parameter is included in the parameter set. The steps of cycling, and determining and the including the second parameter may be repeated until a desired number of cycles/parameters are reached. A retention bake may also be performed on the memory circuit, and a bit error rate resulting from a read operation verified.

Abstract: A system and method for providing memory device readiness to a memory controller is disclosed. One example system includes a channel controller operably connected to a memory controller and a group of flash memory devices. The channel controller may receive, from the memory controller a request for a status of one or more memory devices in the group of flash memory devices. The channel controller may determine the status of the one or more memory devices, the status being determined while the memory controller is permitted to execute one or more other commands related to one or more other memory devices in a different group of memory devices. On determining that the one or more memory devices are in a ready status, the channel controller may provide the ready status to the memory controller.

Abstract: A data storage method, comprising, receiving host data to be written to a plurality of flash storage devices, allocating the host data to one or more data units of a plurality of data units, allocating pad data to one or more data units of the plurality of data units that have not been filled with host data and generating redundant data in a redundant data unit based on the plurality of data units. The method further comprises steps for writing the plurality of data units and the redundant data unit to a stripe across the plurality of flash storage devices, wherein each of the plurality of data units and the redundant data unit is written in the respective flash storage devices at a common physical address.

Abstract: Disclosed is an apparatus and method for determining memory cell bias information for use in memory operations. One or more memory die are selected from a group of memory die, and one or more memory blocks selected from the selected one or more memory die. A group of cells within the selected memory blocks are programmed and cycled. Bias values are generated based on comparing one or more program levels associated with respective wordlines with predetermined programming levels. The bias values are stored lookup table that is configured to be accessible at runtime by a memory controller for retrieval of the bias value during a memory operation.

Abstract: Some embodiments of the disclosed subject matter include an integrated circuit. The integrated circuit includes a solid state device controller configured to control a plurality of flash memory devices, a first set of input output IO pads, coupled to the solid state device controller, arranged as a first pad ring around a perimeter of the integrated circuit, and a second set of IO pads arranged adjacent to at least one side of the first pad ring, wherein one of the second set of IO pads includes a power source node configured to receive a power supply voltage for the solid state device controller, a ground node, and a bond pad configured to receive an external signal.

Abstract: A system and method are disclosed for storing data in a hash table. The method includes receiving data, determining a location identifier for the data wherein the location identifier identifies a location in the hash table for storing the data and the location identifier is derived from the data, compressing the data by extracting the location identifier; and storing the compressed data in the identified location of the hash table.

Abstract: A flash storage device provides direct memory access based on a first communication protocol. A host selects the first communication protocol and provides a request to the flash storage device for a direct memory access. Additionally, the host provides data blocks to the flash storage device for the direct memory access. In the first communication protocol, the host need not provide an address to the flash storage device for the direct memory access. The flash storage device stores the data blocks at sequential addresses starting at a predetermined address in the flash storage device. Another host may then select a second communication protocol and transfer the data blocks in the flash storage by using the second communication protocol.

Abstract: Read signals are obtained from memory cells, and a first read signal and a second read signal are identified, from among the plurality of read signals. The first read signal is associated with a first memory cell in a first word line and the second read signal is associated with a second memory cell in a second word line, and the second word line is adjacent to the first word line. An output for the first memory cell is generated, wherein the output is based on the first and the second read signals.

Abstract: Decoding logic is provided that is operational upon a data buffer to represent a plurality of variable nodes and a plurality of check nodes. For a respective one of the variable nodes, a vector component is selected from a confidence vector associated with the variable node. Using a respective one of the check nodes, a check node return value is calculated based on one or more other vector components from one or more other vectors and one or more vector indices corresponding to the one or more other vector components. The confidence vector is then updated based on the check node return value and an index for the check node return value, and a current state of a memory cell associated with the respective one of the variable nodes is determined based on a location of a primary one of multiple vector components within the updated confidence vector.

Abstract: A method of table journaling in a flash storage device comprising a volatile memory and a plurality of non-volatile data blocks is provided. The method comprises the steps of creating a first copy in a first one or more of the plurality of non-volatile data blocks of an addressing table stored in the volatile memory, writing transaction log data to a second one or more of the plurality of non-volatile data blocks, and updating the first copy of the addressing table based on changes to the addressing table stored in the volatile memory after the second one or more of the plurality of non-volatile data blocks have been filled with transaction log data.

Abstract: Disclosed is an apparatus and method for adjusting operating parameters in a storage device. A controller in a solid state drive monitors current operating conditions of the drive's flash memory, and when the flash memory has been subjected to a predetermined number of program/erase cycles one or more stored bias values are retrieved from a storage location based on the wordline(s) associated with a current memory operation. Parameters of the memory operation are then adjusted based on the retrieved bias values, and the memory operation is performed using the adjusted parameters.

Abstract: A flash controller receives a read request for reading a page of data from the flash memory from a host system, and identifies, in a cache tag table stored in the random access memory, a virtual unit address associated with the page of data. In response to identifying the virtual unit address in the cache tag table, controller determines whether a valid tag line for the page of data is associated with the virtual unit address in the cache tag table. In response to determining that the valid tag line is associated with the virtual unit address in the cache tag table, the controller reads the page of data from the random access memory in accordance with the read request and returns the read data to the host system.

Abstract: Aspects of the subject disclosure relate to a storage device including a flash memory, a controller coupled to the flash memory, wherein the controller is configured to store data to the flash memory and a power arbiter unit coupled to the controller and to the flash memory via a plurality of flash channels, wherein the power arbiter unit is configured to receive a plurality of power requests via one or more of the plurality of flash channels and process the plurality of power requests based on a respective priority identifier associated with each of the plurality of power requests. Additionally, a computer-implemented method and power arbiter unit (PAB) are provided.

Abstract: Disclosed is an apparatus and method for providing memory cell bias information for use in memory operations. One or more memory die are selected from a group of memory die, and one or more memory blocks selected from the selected one or more memory die. A group of cells are programmed within the selected memory blocks, and one or more distributions of cell program levels associated with a group of wordlines are determined. A bias value for each wordline is then generated based on comparing one or more program levels in a distribution of program levels associated with the respective wordline with predetermined programming levels. The bias values are stored lookup table that is configured to be accessible at runtime by a memory controller for retrieval of the bias value during a program or read operation.

Abstract: A system and method for generating reliability information, such as “soft information,” from a flash memory device is disclosed. A plurality of memory cells are read by a data storage controller at a first read level to obtain a plurality of program values. On an error indicator being received in connection with reading the plurality of memory cells, the plurality of memory cells are read one or more times at one or more different read levels to categorize the plurality of memory cells into two or more cell program regions. A confidence value is then assigned to each memory cell based on a corresponding cell program region for the memory cell, the confidence value being representative of a likelihood that the memory cell is programmed to a corresponding program value read at the first read level.