Abstract: Methods and apparatus for encoding, decoding and displaying images in a manner that provides for relatively smooth motion are described. In accordance with the invention a multi-sync display device is used and the refresh rate of the display device is controlled to minimize or avoid judder. Control of the display device refresh rate is performed in various embodiments, as a function of frame display, frame coding, field coding and/or image capture rate information included in an encoded bitstream. Alternatively, the refresh rate of a display is controlled as a function of decoding rate information or other information available from a decoder. In one exemplary embodiment, frames are displayed and the refresh rate of a display device is controlled to be an integral multiple of the indicated frame display rate included in an encoded bitstream.

Abstract: A time domain measurement and control system for a hot wire air flow sensor is disclosed in which the air flow sensor is of the type having a resistive heating element with an input end and an output end. The control system includes a fixed frequency variable width pulse generator which generates a pulse train through the heating element. This pulse train, furthermore, has a first predetermined voltage amplitude. The output voltage amplitude of the pulse train is determined at the outlet end of the heating element while a control circuit varies the duty cycle of the pulse train to maintain the output voltage amplitude at a second predetermined voltage level. The duty cycle of the pulse train is proportional to the air flow rate through the air flow sensor.

Abstract: A layer of material is transformed from a first state to a second state by the application of energy from an energy beam. For example, large direction- and location-controlled p-Si grain growth utilizes recrystallization of amorphous silicon from superpositioned laser irradiation. The superpositioned laser irradiation controls cooling and solidification processes that determine the resulting crystal structure. Specifically, a first laser beam of a first pulse duration is used to melt an amorphous silicon (a-Si) film and to create a temperature gradient. After an initial delay, a second laser beam with shorter pulse duration is superpositioned with the first laser beam. When a-Si is irradiated by the second laser beam, the area heated by the first laser beam becomes completely molten. Spontaneous nucleation is initiated in the supercooled liquid-Si when the liquid-Si temperature drops below the nucleation temperature.

Abstract: Methods and apparatus for improving the quality of images generated by reduced resolution video decoders and new and improved video decoders which produce reduced resolution images are described. Methods and apparatus for identifying conditions within an image which may significantly degrade image quality if particular portions of the image are used by a reduced resolution decoder as reference data are described. One specific embodiment is directed to a new video decoder which decodes portions of a single image, e.g., frame, at different resolutions. Areas of the image along high contrast vertical or horizontal edges are decoded at full resolution while other portions of the same image are decoded at reduced resolution. By decoding and storing portions of reduced resolution images at full resolution for reference purposes, the risk of prediction errors resulting from the use of downsampling on reference frames is reduced.

Abstract: We propose an extension of the view function, called a view with mask, where we can define a mask condition and values for each column that will be applied to the result of query execution. We also provide a set of query rewrite algorithms to implement a view with mask. Then, we define semantics for a selection condition on mask columns, an aggregation on mask columns, and external references for mask conditions. A view with mask can keep a security level, called inference-free against coloring, i.e., if an initial relation is inference-free against coloring, then a result of a query on the relation is also inference-free against coloring.

Abstract: An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.

Abstract: A assembler extended instruction set architecture ISA is formed from a current ISA to which is added new instructions. Assembly of source code listing of a mixture of current and new assembly language instructions is accomplished by preprocessing the source code to create a temporary file that contains the old instructions and data directives for each of the new assembly instructions that have, as the data arguments, the object code equivalent of such new instruction. The temporary file is then applied to the old assembler to produce, for each of the old assembly language instructions, the corresponding object code. The result, after linking, is an executable, machine language program for the new ISA.

Abstract: A negative voltage generator for an integrated circuit includes a charge pump responsive to the current loading on its output terminal. The charge pump is connected to a comparator which compares the output node of the charge pump with a reference potential. The comparator provides an analog output signal to a variable frequency oscillator, which in turn controls the charge pump. Variations in current loading caused the comparator to make appropriate changes in the oscillation frequency.

Abstract: Methods and apparatus for implementing and using a sign(x) function are described. In accordance with the present invention, the sign(x) function is implemented in hardware, e.g., by incorporating a simple circuit of the present invention into a central processing unit (CPU). By taking a hardware approach as opposed to the known software approach to implementing a sign(x) function, the present invention provides for an efficient sign(x) function implementation that is well suited for both SISD and SIMD systems. The hardware required to implement the sign(x) function in accordance with the present invention is relatively simple and allows for the sign(x) function to be determined in a single processor clock cycle. This is in sharp contrast to the plurality of processor clock cycles normally required to determine the sign(x) function in software embodiments. A processor sign(x) command is supported in embodiments where the hardware for performing the sign(x) function is incorporated into a processor.

Abstract: A voltage controlled current source circuit of the present invention includes first reference current coupled to a voltage control node. A current input of a voltage controlled impedance is reproduced at the voltage control node through a current mirror as a second reference current. The voltage resulting from the action of the first and second reference currents is coupled to a voltage control input of the voltage controlled impedance. In one embodiment, a control voltage is provided to the gate of a transistor. The source of the transistor is coupled to the current input of a second voltage controlled impedance circuit to produce an output current at the drain of the transistor. The second voltage controlled impedance circuit has a voltage control input coupled to the voltage control input of the first voltage controlled impedance and to the voltage control node.

Abstract: The present invention addresses decoding and simultaneously displaying multiple images in different windows of a PC or other display device such as a television set. When more than two images are displayed, if the total processing load associated with decoding all of the images to be displayed is over 100%, then decoding priority is decided for each image as a function of display window size. By decoding and displaying images according to this priority, the user can view a desired image, e.g., a main picture image smoothly and comfortably, while other images displayed in smaller sub-windows may only be partially decoded during each frame time. When windows are of the same size, decoding priority is determined between the windows of the same size, as a function of the amount of decoder resources required to decode each image.

Abstract: Methods and apparatus for implementing video decoders at a reduced cost are described. The methods include data reduction techniques, simplified inverse quantization techniques, and dynamically varying the complexity of image enhancement operations, e.g., prediction filtering operations, as a function of whether luminance or chrominance data is being processed. In order to reduce data storage requirements, luminance and chrominance data corresponding to previously encoded images may be stored at different resolutions with, in some embodiments, chrominance data being stored at less than half the resolution of luminance data. In various embodiments, data representing portions of B frames which will not be displayed is identified and discarded, e.g., without performing a decoding operation thereon. Portions of I and P frames which will not be displayed are identified and decoded at a reduced resolution and/or using simplified inverse quantization techniques.

Abstract: Methods and apparatus for implementing and using a sign(x) function are described. In accordance with the present invention, the sign(x) function is implemented in hardware, e.g., by incorporating a simple circuit of the present invention into a central processing unit (CPU). By taking a hardware approach as opposed to the known software approach to implementing a sign(x) function, the present invention provides for an efficient sign(x) function implementation that is well suited for both SISD and SIMD systems. The hardware required to implement the sign(x) function in accordance with the present invention is relatively simple and allows for the sign(x) function to be determined in a single processor clock cycle. This is in sharp contrast to the plurality of processor clock cycles normally required to determine the sign(x) function in software embodiments. A processor sign(x) command is supported in embodiments where the hardware for performing the sign(x) function is incorporated into a processor.

Abstract: Methods and apparatus for improving the quality of images generated by reduced resolution video decoders and new and improved video decoders which produce reduced resolution images are described. Methods and apparatus for identifying conditions within an image which may significantly degrade image quality if particular portions of the image are used by a reduced resolution decoder as reference data are described. In particular, techniques for identifying blocks of pixels, referred to as constant block regions, having approximately the same intensity in terms of luminance values, are discussed. High contrast vertical and/or horizontal edges will cause significant prediction errors in images generated by reduced resolution decoders under certain conditions. Methods for assessing when such conditions exist and a significant prediction error is likely to occur are described. In addition methods and apparatus for minimizing the effect of such prediction errors in downsampling decoders are also described.

Abstract: A system and method that implement a butterfly operation for a fast fourier transform operation in a processor using a matrix-vector-multiply instruction. A first set of inputs to the butterfly operation are defined as r1+j i1 and r2+j i2, and a twiddle factor Wn is defined as Wn=e−j2&pgr;/N=cos(2&pgr;/N)−j sin(2&pgr;/N)=a+jb. The butterfly operation stores r1, i1, r2 and i2 in a first set of registers and stores the twiddle factor in matrix registers. The matrix-vector-multiply instruction is executed between the matrix registers and the first set of registers.

Abstract: Methods and apparatus for providing speech recognition capability to callers in a cost efficient manner as part of one or more telephone services are described. Multiple speech recognition units with differing capabilities and therefore implementation costs are provided. Calls are assigned to speech recognition circuits throughout a call based on a signal such as a service type identifier indicating the type of service to be provided to the caller. During different phases of a call different speech recognition units may be used. In addition, different amounts of speech recognition processing capability may be allocated to service a call at different points during a call. In this manner efficient use of available speech recognition resources can be achieved.

Abstract: Methods and apparatus for implementing and using a sign(x) function are described. In accordance with the present invention, the sign(x) function is implemented in hardware, e.g., by incorporating a simple circuit of the present invention into a central processing unit (CPU). By taking a hardware approach as opposed to the known software approach to implementing a sign(x) function, the present invention provides for an efficient sign(x) function implementation that is well suited for both SISD and SIMD systems. The hardware required to implement the sign(x) function in accordance with the present invention is relatively simple and allows for the sign(x) function to be determined in a single processor clock cycle. This is in sharp contrast to the plurality of processor clock cycles normally required to determine the sign(x) function in software embodiments. A processor sign(x) command is supported in embodiments where the hardware for performing the sign(x) function is incorporated into a processor.

Abstract: A receiver arranged to receive and store broadcast data transported by elementary stream of a multiplexed and modulated digital television signal in a rewritable memory during a low power consumption mode for later recall by a user of the receiver. For recall, the receiver is fully energized, and the receiver is further arranged to transfer the broadcast data stored in the rewritable memory to a receiver storage device for further processing of the data under control of the user.

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.