Abstract: A server system has, in addition to extensibility of scale-out type of a braid server system, extensibility of scale-up type by making SMP coupling among nodes. Each node has a unit for SMP coupling to other nodes. A module management unit responds to system configuration information to switch between a mode in which the node operates singularly as a braid server and a mode in which the node operates as a constituent module of an SMP server. Links among individual nodes are laid through equidistant wiring lines on a back plane and additionally a loop wiring line having a length equal to that of the inter-node link on the back plane is also laid in each node, thereby setting up synchronization among the nodes. Synchronization of reference clocks for SMP coupled nodes is also established.

Abstract: An input interface segments a variable length packet into plurality of fixed length cells and generates an internal switching information based on the header information of the variable length packet. The input interface transmits the information to a switch and, after that, transmits the cells as the following cells of the information to the switch. The switch performs switching processing to the succeeding cells based on the information. Therefore, the information is not added to the cells. When an input interface starts to transmit cells generated from a packet to its destination output interface through the switch, the switch is reserved until all the cells arrive at the output interfaces.

Abstract: A server system has, in addition to extensibility of scale-out type of a braid server system, extensibility of scale-up type by making SMP coupling among nodes. Each node has a unit for SMP coupling to other nodes. A module management unit responds to system configuration information to switch between a mode in which the node operates singularly as a braid server and a mode in which the node operates as a constituent module of an SMP server. Links among individual nodes are laid through equidistant wiring lines on a back plane and additionally a loop wiring line having a length equal to that of the inter-node link on the back plane is also laid in each node, thereby setting up synchronization among the nodes. Synchronization of reference clocks for SMP coupled nodes can be is also established.

Abstract: A sealing structure for multi-chip modules stable in cooling performance and excelling in sealing reliability is to be provided. The under face of a frame 5 compatible with a wiring board 1 in thermal expansion rate is fixed with solder 8 to the face of the wiring board 1 for mounting semiconductor devices 2; a rubber O-ring 15 is placed between the upper face of the frame 5 and the under face of the circumference of an air-cooled: heat sink 7; the plastic member 6 making possible relative sliding is placed between the upper face of the circumference of the heat sink 7 and the upper frame 10; the upper face of a plastic member 6 is restrained with the inside middle stage of an upper frame 10; and the lower part of the upper frame 10 and the frame 5 are fastened together with bolts 9.

Abstract: Architecturally complicated computers require functionally complicated compiler. For such a compiler, the present invention provides an automatic compiler test program generation method capable of reducing the man-hour required to prepare a test program and testing many aspects of the compiler. By a random number-used method, a plurality of program cells are selected from a set of program cells each of which may form an element of a test program. The selected program cells are combined into a test program.

Abstract: A system for use with communications according to TCP, or a similar protocol, includes a sender host, one or more routers, and a destination host. Each router includes means for generating acknowledgement packets and translating addresses associated with data packets. When a data packet is received by a router, an acknowledgement packet is returned with a source address corresponding to the router and a destination address corresponding to the sender host. The sender host perceives the acknowledgement packet as having been sent by the destination host. As the acknowledgment packet is sent by the router, and not the destination packet is sent by the router, and not the destination host, this system allows acknowledgment packets to be received on a shorter timescale, reducing the effects of a link delay. Although the route between the sender host and the destination host is divided into multiple connections, the hosts perceive a single, conventional connection.

Abstract: A delay diagnosis method is proposed that can avoid design steps from being retraced or repeated uselessly due to defective delay when we design a semiconductor integrated circuit including a plurality of blocks. This delay diagnosis method has the steps of inputting logic information and floor plan information, finding the number of start points connected to the end point of a path from the logic information, computing the logic stage number of the path from the number of start points, finding block-to-block distances from the floor plan information, computing intra-block delays from the logic stage number and gate unit-value delays, computing inter-block delays from the block-to-block distances and routing unit-value delays, and diagnosing if the delay of the path after logic synthesis can be converged within a target path delay from the relation among the computed intra-block delays and inter-block delays and the target path delay.

Abstract: The present invention concerns an information access device for utilizing a supposed information service, which possesses an information-inputting device. The information access device according to one embodiment of the present invention comprises a usage discrimination part which judges whether the information-inputting device is utilized for said intended information service or unintended usage, based on prescribed information from said information inputting device.

Abstract: Each flip-flop-to-flip-flop path delay and a target machine cycle obtained in the stages of physical design and packaging design are used as input, and with respect to a path in which the path delay is not less than the target machine cycle, a closed loop including the path is extracted, and the timing of a clock signal of each flip-flop is adjusted so as to permit data transmission along the closed loop in a required cycle-number. At this time, a path along which data transmission is impossible in the target machine cycle or a closed loop including the path is listed in order to be modified. As methods of supplying a clock signal to each flip-flop, a plurality of methods different in the adjustable range of clock timing are combined and used.

Abstract: A semiconductor integrated circuit test method which reduces the required data volume for testing and efficiently detects faults in a circuit to be tested, the method comprising means 110 to generate identical pattern sequences repeatedly and means 120 to control flipped bits in pattern sequences, in order to generate neighborhood pattern sequences and use the neighborhood patterns to test the circuit under test 130. The neighborhood patterns include, in whole or in part, such pattern sequences as ones without flipped bits, ones with all or some flipped bits in one pattern and ones with all or some flipped bits in consecutive patterns or patterns at regular intervals, the interval being equivalent to a given number of patterns.

Abstract: The present invention relates generally to D.C. power supplies and more particularly to overvoltage protection in one or more D.C. power supply circuits, where a plurality of D.C. power supplies may be connected together to supply power to an electronic system. In one embodiment a D.C. power supply circuit is provided which, when used with the plurality of D.C. power supply circuits connected in parallel, is capable of stopping only the power supply circuit having run into an overvoltage state with minimal effect on the other D.C. power supply circuits. Thus power to the load is continued.

Abstract: According to the invention, techniques for automatically adjusting for astigmatism in a charged particle beam apparatus. Embodiments according to the present invention can provide a charged particle beam apparatus and an automatic astigmatism adjustment methods capable of automatically correcting astigmatism and a focal point in a relatively short period of time by finding a plurality of astigmatism correction quantities and a focal point correction quantity in a single operation from a relatively small number of 2 dimensional images. Specific embodiments can perform such automatic focusing while minimizing damages inflicted on subject samples. Embodiments include, among others, a charged particle optical system for carrying out an inspection, a measurement and a fabrication with a relatively high degree of accuracy by using a charged particle beam.

Abstract: According to the present invention, techniques for performing real time backup of data in the presence of a pending hazard, such as a natural disaster, or the like. Embodiments can provide data storage controllers, networked data storage systems, methods and the like, that detect imminent hazardous conditions and alter backup behavior to provide greater integrity of backed up data. In a representative embodiment according to the present invention, update of the primary data is temporarily suspended after the recognition of a probable occurrence of a hazardous event. By suspending updating the primary data temporarily, the increase of un-updated secondary data can be prevented, so that lost data is decreased. Then, the un-updated secondary data can be updated quickly or exclusively, in order to avoid un-updated secondary data.

Abstract: An input interface segments a variable length packet into plurality of fixed length cells and generates an internal switching information based on the header information of the variable length packet. The input interface transmits the information to a switch and, after that, transmits the cells as the following cells of the information to the switch. The switch performs switching processing to the succeeding cells based on the information. Therefore, the information is not added to the cells. When an input interface starts to transmit cells generated from a packet to its destination output interface through the switch, the switch is reserved until all the cells arrive at the output interfaces.

Abstract: A packet forwarding apparatus provided with a plurality of line interface units, comprises a routing processing unit for referring to a routing table, based on header information of received packet to specify one of output lines to output the received packet, a flow detection unit for referring to an entry table, in which a plurality of entries with flow conditions and control information are registered, to retrieve control information defined by the entry with a flow condition which coincides with that of the header information of the received packet, and a packet forwarding unit for transferring the received packet to one of the line interface units connected to the output line specified by the routing processing unit.

Abstract: In a high speed multicast route searching method of searching information of a transmission port to which a received multicast packet is next transferred: a route address is formed by coupling a receiver address and a sender address in this order; one p-th power-of-2-branch tree node is configured by a collection of one two-branch tree node and two-branch tree nodes of p−1 stages totalling ((p-th power of 2)−1) nodes just under the one two-branch tree node to form a p-th power-of-2-branch tree which is stored in a memory; not one bit but consecutive p bits of the route address coupling the receiver address and sender address in a received multicast packet in this order are checked at the same time; and in accordance with the values of the consecutive bits, a search tree stored in the memory is searched. In this manner, a search process can be completed by tracing nodes (the number of bits of a search key divided by p) times at a maximum, independently from the number of entries.

Abstract: According to the present invention, techniques for performing real time backup of data in the presence of a pending hazard, such as a natural disaster, or the like. Embodiments can provide data storage controllers, networked data storage systems, methods and the like, that detect imminent hazardous conditions and alter backup behavior to provide greater integrity of backed up data. In a representative embodiment according to the present invention, update of the primary data is temporarily suspended after the recognition of a probable occurrence of a hazardous event. By suspending updating the primary data temporarily, the increase of un-updated secondary data can be prevented, so that lost data is decreased. Then, the un-updated secondary data can be updated quickly or exclusively, in order to avoid un-updated secondary data.

Abstract: A packet forwarding apparatus provided with a plurality of line interface units, comprises a routing processing unit for referring to a routing table, based on header information of received packet to specify one of output lines to output the received packet, a flow detection unit for referring to an entry table, in which a plurality of entries with flow conditions and control information are registered, to retrieve control information defined by the entry with a flow condition which coincides with that of the header information of the received packet, and a packet forwarding unit for transferring the received packet to one of the line interface units connected to the output line specified by the routing processing unit.

Abstract: A network relaying apparatus and method for routing and transferring packets at high speed. A transfer engine stores the packets received through a network interface in a packet buffer, and stores the header information in a header RAM. A search engine searches the transfer control information including the transfer destination information and the action information in accordance with the header information, and writes it in the header RAM. The transfer engine produces an output packet based on the information stored in the packet buffer and the header RAM and outputs it to the transfer destination. A switch switches the output packet to the routing process of the destination. The transfer engine executes the receiving process and the transmission process, and the search engine executes the input search process and the output search process. Each of these processes is executed by pipelining control using a required table independently.

Abstract: A network relaying apparatus and a network relaying method for securing a high communication quality (QoS), a high reliability and security. A transfer engine stores the packets received through at least a network interface in a packet buffer, and the header information in a header RAM. A search engine searches for the transfer control information such as the destination information and the action information based on the header information, and writes them in the header RAM. The transfer engine prepares an output packet based on the information stored in the packet buffer and the header RAM, and outputs the output packet to the destination. A switch switches the output packet to the routing processor of the destination. Each header RAM is asynchronously accessible independently of the packet buffer and suppresses the competition for access between the transfer engine and the search engine.