Abstract: The present invention concerns an information access device for utilizing a supposed information service, which possesses an information-inputting device. The information access device according to one embodiment of the present invention comprises a usage discrimination part which judges whether the information-inputting device is utilized for said intended information service or unintended usage, based on prescribed information from said information inputting device.

Abstract: A network relaying apparatus and method for high quality transfer of packets under stable quality-of-service (QoS) control. A transfer engine stores the packets received through a network interface, in a packet buffer, and the header information in a RAM. A search engine searches the transfer control information including the transfer destination information and the action information according to the header information and writes the resulting information in the header RAM. The transfer engine produces an output packet based on the information stored in the packet buffer and the header RAM and outputs it to the transfer destination. A switch operates to switch the output packet to the routing processor of the destination. The QoS control is performed at each of a plurality of points including the input-side routing processor, the output-side routing processor 10 and the switch.

Abstract: A network relaying apparatus and method for detecting a flow at high speed and performing a variety of control operations including quality-of-service (QoS) control and filtering at high speed. A transfer engine stores the packet received through a network interface, in a packet buffer, and stores the header information in a header RAM. A search engine searches the transfer control information including the transfer destination information and the action information according to the header information, and writes it in the header RAM. The transfer engine produces an output packet based on the information stored in the packet buffer and the header RAM and outputs it to the transfer destination. A switch operates to switch the output packet to the routing processor of the final destination.

Abstract: A network relaying apparatus and method for routing and transferring packets at high speed. A transfer engine stores the packets received through a network interface in a packet buffer, and stores the header information in a header RAM. A search engine searches the transfer control information including the transfer destination information and the action information in accordance with the header information, and writes it in the header RAM. The transfer engine produces an output packet based on the information stored in the packet buffer and the header RAM and outputs it to the transfer destination. A switch switches the output packet to the routing process of the destination. The transfer engine executes the receiving process and the transmission process, and the search engine executes the input search process and the output search process. Each of these processes is executed by pipelining control using a required table independently.

Abstract: There is provided a semiconductor integrated circuit device for realizing in the higher accuracy the verification of a plurality of operations of a clock generation circuit to form an internal clock signal and enabling verification for various performances of the internal clock signal generation circuit while simplifying the structure thereof. In such semiconductor integrated circuit device, a measuring circuit for conducting at least two kinds of measurements among the measurements of lock time until the predetermined internal clock signal corresponding to the input clock signal can be obtained, the maximum frequency of the internal clock signal and jitter of the internal clock signal is provided to the clock generation circuit to form the internal clock signal corresponding to the input clock signal inputted from an external terminal. Thereby, operations of the clock generation circuit can be verified with higher accuracy within the semiconductor integrated circuit device.

Abstract: Each of a plurality of data processing units that form a network relaying apparatus has a memory controller, a network controller, a processor, and independently accessible first and second memories. The memory controller includes a header information register for storing header information such as a header start position in a packet and a header length; a header position detection circuit for detecting a header position in the packet based on the header information contained in the header information register; and an inter-data processing unit transfer circuit for sending and receiving a packet to and from another data processing unit. The data processing unit stores into the first memory a packet received from the network or a packet transferred from another data processing unit, and at the same time stores only a header portion of the packet into the second memory.

Abstract: Each of processing nodes and switching apparatuses constituting a parallel processor system is provided with data transmitting/receiving apparatuses 100 and 200. The data transmitting/receiving apparatus 100, in response to an instruction from a processor P within its own node, transmits data stored in a transfer data buffer 110 to the data transmitting/receiving apparatus 200 of a switching apparatus connected thereto. The data transmitting/receiving apparatus 200 receives data that are transferred, and stores them into a transfer data buffer 210. If any error in receive data is detected by an error detector 214 of the data transmitting/receiving apparatus 200, a retransmission request signal 10 is issued from a retransmission control circuit 215 to the retransmission control circuit 114 of the transmitting apparatus 100. The retransmission control circuit 114, upon receiving the retransmission request signal 10, instructs a data transmission control signal 112 to execute retransmission.

Abstract: A packet switching is performed according to a routing information for relaying particular packets which is produced by the route computation based on the information of a received packet and the kept parts-of-routing-information useful as a basis for the route computation. At this time, the route through which the packet is relayed is determined on the basis of the kept parts-of-routing-information before the route computation. Then, the received packet is relayed according to the determined route. Next, a new routing information is produced by the route computation based on the information of the received packet and the parts-of-routing-information. Thereafter, the succeeding packets of the same route are relayed on the basis of the new routing information.

Abstract: An input/output processing system wherein even when one of channel processors has become faulty, channels so far controlled by the faulty channel processor can be controlled by the other normal channel processor, so that input/output devices can be continuously used. The system is configured such that channels (CHs) so far connected only to a first channel processor (CHP) are also connected to a second channel processor (CHP), and channels (CHs) so far connected only to the second channel processor (CHP) are also connected to the first channel processor (CHP). Thereby the first and second channel processors (CHPs) can be multiplexedly connected to the channels (CHs) to allow the channel processors (CHPs) to control all the channels (CHs).

Abstract: An LSI having a logic circuit and a test circuit is provided with a first register which is connected between an LSI input/output pin and the logic circuit and has a first input terminal to be outputted from the first register in accordance with a system clock signal and a second input terminal, a second register which has a first input terminal inputted with an output of the first register and a second input terminal inputted with scan-in data and an output of which is connected to the second input terminal of the first register, a selector circuit which is connected to one of the first input terminal of the second register and the second terminal of the first register and selects one of a signal relating to scan-out data and an output signal of the other register so that the selected signal is inputted to the one input terminal, and a third register which receives an output of the second register and provides the received output as scan-out data in accordance with another clock signal.

Abstract: An electronic device has a frame and a back board having plural logical units and power supply units mounted thereon. The logical units and the power supply units are alternately located on both sides of the back board in the center of the frame so that the power supply units mounted on one side of the back board may feed a power to the closest logical units mounted on the other side. Further, the air flow paths to be circulated through the logical units and the power supply units are formed so that each unit may be efficiently cooled by the air fed by an air fan unit. As a result, the feeding voltage becomes uniform and the cooling efficiency is improved.

Abstract: Disclosed is a printing system comprising a primary system and a printer connected thereto. To enhance the usability of a sorting operation for printed matters, the primary system includes a sorting instructing means for transmitting, to the printer, an instruction regarding contents of printing job separation marks for indicating a separation between jobs before printing job data; and the printer includes a means for analyzing a sorting instruction supplied from the primary system, and a means for executing a sorting operation in accordance with the analyzed result.

Abstract: A very-small-signal amplifier is capable of amplifying very small signals with high sensitivity up to high frequencies while simplifying the circuit, and a magnetic disk storage apparatus realizes a reading operation over a wide band up to high frequencies with high sensitivity. The signal amplifier is a modified differential circuit including a first transistor of a first conductivity type and a second transistor of a second conductivity type each having a control terminal, a terminal of the input side and a terminal of the output side. The terminals on the input side are connected in common, and a current corresponding to the voltage difference across the control terminals is allowed to flow. A very small voltage signal generated by an input signal source is applied to the control terminal of said first transistor. A bias voltage is applied to the control terminal of the second transistor.

Abstract: An information processing unit having a bus controller connected to a plurality of different shared buses which can independently control the different shared buses, and a double adaptor connected to the different shared buses which can independently control the different shared buses, wherein first and second ones of the shared buses are independently controlled to send data from the bus controller to the double adaptor, and from the double adaptor to the bus controller, respectively.

Abstract: A personal computer has a print image developing means and a data compression means including a fixed rate compression. A color printer has a data extension means, a color correction means, a gamma correction means, a first halftoning means, an image area segmentation means, and a second halftoning means. The transmission time of a print image can be shortened necessarily to less than a constant time, and further, since an enormous memory for extension is unnecessary, a low cost printer can be provided.

Abstract: A very-small-signal amplifier is capable of amplifying very small signals with high sensitivity up to high frequencies while simplifying the circuit, and a magnetic disk storage apparatus realizes a reading operation over a wide band up to high frequencies with high sensitivity. The signal amplifier is a modified differential circuit including a first transistor of a first conductivity type and a second transistor of a second conductivity type each having a control terminal, a terminal of the input side and a terminal of the output side. The terminals on the input side are connected in common, and a current corresponding to the voltage difference across the control terminals is allowed to flow. A very small voltage signal generated by an input signal source is applied to the control terminal of said first transistor. A bias voltage is applied to the control terminal of the second transistor.

Abstract: An input/output data transfer system capable of integrating input/output data transfer on a plurality of input/output interface cables into data transfer on a single serial input/output interface cable for substantially reducing the number of input/output interface cables required for a host computer system. A multiplexer channel device is provided with a plurality of channels which serve as logical channels corresponding to conventional physical channel paths from a viewpoint of an operating system running on the host computer system. A multiplexer port device is provided with a plurality of input/output ports on a switching device or input/output device, each of these channels and ports shares a large-capacity input/output interface, and a channel path multiplexing function is performed for enabling frame-by-frame multiplexing and simultaneous input/output operations on plural channels.

Abstract: A communication network system includes a plurality of networks interconnected via a plurality of relaying stations each performing a program controllable process to relay communication data, the program controllable process comprises a routing table having route information for determining a route to transfer the communication data, a learning processing unit exchanging the route information contained in the routing table among the individual relaying stations in accordance with the route information of the routing table to acquire the route information by the exchange, and a route information transform processing unit for transforming the route information contained in the routing table as acquired by the learning step into route information non-exchangeable among the individual relaying stations.

Abstract: An interrupt processing system and method for an information processing system of pipeline control type are disclosed. The occurrence of an exception is detected for each plurality of instructions to be processed in parallel. The occurrences of exceptions, when detected for a plurality of the instructions to be processed in parallel, are reported collectively according to each cause of the exceptions. In the case where the occurrences of exceptions are reported for a plurality of the instructions to be processed in parallel by an exception reporting unit, an interrupt request is issued. In response to the interrupt request, the pipeline processing is restored by an instruction control unit to the state before execution of the leading one of the plurality of the instructions to be processed in parallel for which the occurrences of exceptions are detected, and the instructions are reexecuted one by one sequentially from the leading one of the plurality of instructions through the instruction control unit.

Abstract: An arithmetic method and apparatus for executing a TMH (Test under Mask High) and a TML (Test under Mask Low) instruction. This apparatus comprises a circuit for detecting that the result of an AND operation performed on a test mask and an operand is "0", which represents the condition for setting a condition code at "0", a circuit for detecting an operand bit corresponding to the leftmost bit of the test mask which is the condition for setting the condition codes at "1" and "2", a circuit for detecting that the result of an OR operation performed on an inverted test mask and the operand is all zeros, which is the condition for setting the condition code at "3", and a circuit for producing a proper condition code based on the outputs of those circuits.