Patents Assigned to Hitachi, Ltd.
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Patent number: 6387235Abstract: An apparatus for the separation and fractionation of differentially expressed gene fragments includes a separating means including a capillary filled with a separation medium to separate DNA fragments by electrophoresis, a sampling means including sampling vessels to fractionate and sample the separated DNA fragments, according to their size, a transferring means to transfer buffer solution containing the separated DNA fragments to the sampling means, and a control means to control the sampling means based on a signal gained by detecting means, wherein a voltage for the electrophoresis and a length of the capillary are adjusted such that a spread in time of the separated DNA fragments caused by the transferring means during the transfer of the separated DNA fragments to the sampling vessels is smaller than a difference in separation time of the DNA fragments in the separating means.Type: GrantFiled: August 30, 1999Date of Patent: May 14, 2002Assignee: Hitachi, Ltd.Inventors: Takashi Irie, Hideki Hasegawa, Hideki Kambara, Ken Ninomiya
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Patent number: 6389523Abstract: A comparator is constituted such that a hit signal &phgr;hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.Type: GrantFiled: April 25, 2000Date of Patent: May 14, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Co., Ltd.Inventors: Yasuhisa Shimazaki, Seiichi Nagata, Katuhiro Norisue, Koichiro Ishibashi, Junichi Nishimoto, Shinichi Yoshioka, Susumu Narita
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Patent number: 6389531Abstract: A processor is provided with an improved instruction buffer, branch target instruction memory, branch target address memory and instruction decoder adapted for handling branch instructions so as to reduce latencies. A branch operation uses both a program branch control instruction (executed in advance to determine the branch target instruction address) and either a conditional or unconditional branch instruction associated with a conditional/unconditional branch target instruction respectively. The conditional/unconditional branch instruction and the program branch control instruction both include separate prediction indicators used by the instruction decoder for initiating a loading and speculatively pre-loading of instructions for execution in the processor.Type: GrantFiled: October 17, 2000Date of Patent: May 14, 2002Assignee: Hitachi, Ltd.Inventors: Naohiko Irle, Tony Lee Werner
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Patent number: 6389063Abstract: The signal x to be transmitted is converted to the redundant code f(x) by the redundancy coder 6 and transmitted via the isolating capacitor 2 of the isolator 50. When the signal f(x) redundancy-coded and transmitted is the coded word f(xi), the decoder 7 outputs xi which is inferred as an equivalent original signal and when an error occurs and the signal f(x) does not match the coded word f(xi), the decoder 7 corrects the error and outputs xi which is inferred as an original signal.Type: GrantFiled: October 30, 1998Date of Patent: May 14, 2002Assignee: Hitachi, Ltd.Inventors: Nobuyasu Kanekawa, Kazuo Kato, Yasuyuki Kojima, Seigoh Yukitake
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Patent number: 6388976Abstract: A dichroic mirror of a polarized beam splitter is installed between a mirror and an objective lens as a beam synthesize/split means, in an optical system corresponding to a second dick and an optical system corresponding to a first disk arranged so as to form a two-layer structure. The dimension of the optical head in the width, length, and thickness directions are designed moderately.Type: GrantFiled: February 29, 2000Date of Patent: May 14, 2002Assignees: Hitachi, Ltd., Hitachi Media Electronics Co., Ltd.Inventors: Shinji Fujita, Hidenori Shinohara, Toshio Sugiyama, Nobuo Imada, Yukio Fukui
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Patent number: 6388562Abstract: A reader/writer (RW) requires identification of anti-collision techniques used by IC cards (A, B, C, and D). The IC cards implement answers to the anti-collision technique identification requirement by the reader/writer at different timings respectively for respective IC cards among the IC cards which use different anti-collision techniques respectively. The reader/writer requires identifications of types of the IC cards in dependence upon the anti-collision techniques in response to the answers by the IC cards. The IC cards return identification data thereof in response to the card type identification requirements by the reader/writer for respective IC cards among the IC cards which use different anti-collision techniques respectively. The reader/writer identifies the types of the IC cards in response to the identification data of the respective IC cards.Type: GrantFiled: January 12, 1999Date of Patent: May 14, 2002Assignees: Denso Corporation, Nippon Telegraph and Telephone Corporation, Hitachi Ltd., Tokin CorporationInventors: Masahiro Takiguchi, Kiyoshi Takahashi, Tatsuya Hirata, Shigeru Date, Hisanobu Dobashi, Shinji Nishimura, Ryouzo Yoshino, Tomoaki Ishifuji, Hiromi Sato, Toru Miura
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Patent number: 6389439Abstract: A different phase type is specified toward each of a plurality of processors constituting a parallel computer, thereby, in a changeable manner, generating M sequence random numbers having the phase type. An information inputting unit inputs, into a random-number generating process unit, the number of the processors used in a parallel processing, the number of the random numbers to be generated by a single processor, the number of the phase types of the random numbers to be generated, and phase type information for each processor. The random-number generating process unit includes a phase-type management-table creating process unit, an initial-value table generating process unit, and a random-number generating calculation unit.Type: GrantFiled: July 14, 1999Date of Patent: May 14, 2002Assignee: Hitachi, Ltd.Inventors: Saori Mitsunaga, Nobuhiro Ioki
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Patent number: 6389413Abstract: A text cataloging method includes a step of cataloging already-analyzed-text data obtained from an analysis of a logical structure of a text to be cataloged in a text database, a step of creating a structure index by sequentially superposing logical structures of texts to be cataloged, wherein a single metaelement is used for representing a group of elements in the texts having the same position of appearance in one of the texts and the same element type, a single piece of meta-character-string data is used for representing a group of pieces of character-string data in the texts having the same position of appearance in one of the texts, and a context identifier is assigned to each metanode composing a tree-like structure of the structure index for uniquely identifying the metanode; a step of generating structured-full-text data composed of definitions of associative relations between all pieces of character-string data included in already-analyzed-text data of each text to be cataloged, and context identifieType: GrantFiled: March 15, 2001Date of Patent: May 14, 2002Assignee: Hitachi, Ltd.Inventors: Toru Takahashi, Hisamitsu Kawaguchi, Noriyuki Yamasaki
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Patent number: 6388987Abstract: An information recording medium having spiral or concentric-shaped groove structure along a track formed on a disk-like substrate. The medium has the groove structure wobbled in a radius direction of the medium and the track is divided into a plurality of recording units in the track direction by at least one radial boundary. At least two adjacent recording units in the track direction of the medium comprise one zone and the medium includes a plurality of the zones. The groove structure included in the adjacent recording units within any zone has substantially the same number of wobbling.Type: GrantFiled: January 18, 2001Date of Patent: May 14, 2002Assignee: Hitachi Ltd.Inventors: Harukazu Miyamoto, Yoshio Suzuki, Motoyuki Suzuki, Hisataka Sugiyama, Hiroyuki Minemura, Tetsuya Fushimi, Nobuhiro Tokushuku
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Patent number: 6388382Abstract: The main purpose of the present invention is to suppress deposition of byproducts on an inner wall of a vacuum chamber during wafer processing using plasma generated by an inductive coupling antenna and an electrostatic capacitive coupling antenna which are connected in series at a connection point. Deposition of byproducts on the inner wall of the vacuum chamber can be suppressed by grounding the connection point of the inductive coupling antenna and the electrostatic capacitive coupling antenna via a variable-impedance load and varying an impedance of the variable-impedance load, thereby controlling a ratio of plasma produced in the chamber by electrostatic capacitive coupling discharge.Type: GrantFiled: March 8, 2000Date of Patent: May 14, 2002Assignee: Hitachi, Ltd.Inventors: Akira Doi, Ken Yoshioka, Manabu Edamura, Hideyuki Kazumi, Saburou Kanai, Tsutomu Tetsuka, Masatsugu Arai, Kenji Maeda, Tsunehiko Tsubone
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Patent number: 6388941Abstract: Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.Type: GrantFiled: July 13, 2001Date of Patent: May 14, 2002Assignees: Hitachi, Ltd., Hitachi, ULSI Systems Co., Ltd.Inventors: Hiroshi Otori, Hiroki Fujisawa, Minoru Ebihara, Seiji Narui, Masanori Isoda, Akira Ohta
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Patent number: 6387632Abstract: Different probes each having a specific base sequence are immobilized to each of independent areas formed on the surface of a substrate, complementary polynucleotides in a sample solution are hybridized to the probes, and each of the independent areas on the substrate is heated and then cooled in sequence, and hence the solution is recovered to extract different polynucleotides separately corresponding to individual probes.Type: GrantFiled: February 23, 2001Date of Patent: May 14, 2002Assignee: Hitachi, Ltd.Inventors: Kenji Yasuda, Kazunori Okano, Hirokazu Kato
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Patent number: 6388804Abstract: Disclosed is an optical amplifier which is smaller in power consumption and number of component parts, simpler in structure, and rid of wavelength dependency of gain against the variation of input light power and temperature. The optical amplifier has a characteristic information table which stores data of a proper curve indicative of the relation between the pumping light power and output light power of the optical amplifying medium at a constant gain tilt of wavelength-multiplexed signal light, and a pumping light controller which controls the pumping power such that the output light power and pumping light power of the optical amplifying medium are related to lie on the proper curve.Type: GrantFiled: March 16, 2001Date of Patent: May 14, 2002Assignee: Hitachi, Ltd.Inventor: Toshiki Sugawara
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Patent number: 6388474Abstract: For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.Type: GrantFiled: May 21, 2001Date of Patent: May 14, 2002Assignee: Hitachi, Ltd.Inventors: Yasuhiko Sasaki, Kazuo Yano, Shunzo Yamashita, Koichi Seki
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Publication number: 20020053247Abstract: An automatic transmission has a first axis (input axis) 102 for inputting the power, a second axis (output axis or couner axis) 103 for outputting the driving force source, at least one or more first gear group which consists of drive gears 111, 112 fixed on the first axis, and a driven gear 122 provided so as to engage or run idle with respect to the second axis with being engaged with the drive gear, and at least one or more second gear group which consists of driven gears 123, 124, 125 fixed on the second axis, and a drive gear 114, 115 provided so as to engage or run idle with respect to the first axis with being engaged with the driven gear. The automatic transmission further comprises a torque transferring mechanism 140 for transfering the torque between said driven gear which can run idle with respect to the second axis and the driven gear fixed to the second axis.Type: ApplicationFiled: November 7, 2001Publication date: May 9, 2002Applicant: HITACHI, LTD.Inventors: Takashi Okada, Toshimichi Minowa, Mitsuo Kayano, Tatsuya Ochi, Hiroshi Sakamoto, Hiroshi Kuroiwa, Naoyuki Ozaki
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Publication number: 20020056079Abstract: A method, by which if a reissued smart card is issued based on an old smart card, the application program loaded in the old smart card is smoothly reloaded in the reissued smart card, is disclosed. Its specific configuration will be described as below. A method for loading an application program in a smart card comprises the steps of: in response to a request for loading one application program for a smart card in the smart card that has been reissued based on an old smart card, judging whether or not said one application program was loaded in the old smart card, according to a relationship between a card id of the reissued smart card and a card id of the old smart card; and if it is found out that said one application program was loaded, loading said one application program in the reissued smart card.Type: ApplicationFiled: August 29, 2001Publication date: May 9, 2002Applicant: Hitachi, Ltd.Inventors: Akiko Sato, Yusuke Mishina, Minoru Ashizawa, Masaru Ohki, Nikkou Kaku, Shohei Takeuchi, Hirohiko Kurokawa, Shinichi Hirata
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Publication number: 20020054511Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.Type: ApplicationFiled: November 27, 2001Publication date: May 9, 2002Applicant: Hitachi, Ltd.Inventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
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Publication number: 20020054118Abstract: A simple and easy-to-memorize operation method for a scheduling management system is provided to perform main tasks such as referring to schedules of a selected member or a selected date. A software component indicating a schedule, a member, or a date is moved to any one of components constituting a GUI screen, and when the software component is superposed upon another component, the motion destination component constituting the GUI screen judges the type of the superposed software component to select a process to be performed. Main tasks can be performed by a simple operation method through superposition of software components.Type: ApplicationFiled: August 14, 2001Publication date: May 9, 2002Applicant: Hitachi, Ltd.Inventors: Hiroshi Ishizaki, Norihito Suganuma
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Publication number: 20020053748Abstract: The present invention provides a method of manufacturing halftone phase shift masks in less steps to save time and cost and to increase the yield, and a halftone phase shift mask with higher phase—and size controllability. To achieve this, the halftone phase shift mask includes a structure having a shade band of resist film formed on the halftone film delineating fine patterns and around the area of fine pattern.Type: ApplicationFiled: March 16, 2001Publication date: May 9, 2002Applicant: Hitachi, Ltd.Inventors: Toshihiko Tanaka, Norio Hasegawa
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Publication number: 20020055261Abstract: In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved.Type: ApplicationFiled: November 30, 2001Publication date: May 9, 2002Applicant: Hitachi, Ltd.Inventors: Akio Nishida, Kikuo Kusukawa, Toshiaki Yamanaka, Natsuki Yokoyama, Shinichiro Kimura, Norio Suzuki, Osamu Tsuchiya, Atsushi Ogishima