Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract: A microcomputer CMU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract: A network system includes a plurality of networks, a first internetwork apparatus having a plurality of first ports each connected to the plurality of networks, a second internetwork apparatus having a plurality of second ports each connected to the plurality of networks, and a data transmission path connected to the first and second internetwork apparatuses to transmit data mutually between the first and second internetwork apparatuses. In the normal state, each of the plurality of first ports is caused to be able to transmit and receive data to and from one of the plurality of networks and the plurality of second ports are caused not to be able to receive data from the plurality of networks and to be able to transmit data to the plurality of networks.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A network system includes a plurality of networks, a first internetwork apparatus having a plurality of first ports each connected to the plurality of networks, a second internetwork apparatus having a plurality of second ports each connected to the plurality of networks, and a data transmission path connected to the first and second internetwork apparatuses to transmit data mutually between the first and second internetwork apparatuses. In the normal state, each of the plurality of first ports is caused to be able to transmit and receive data to and from one of the plurality of networks and the plurality of second ports are caused not to be able to receive data from the plurality of networks and to be able to transmit data to the plurality of networks.

Abstract: A method of manufacturing a semiconductor integrated circuit device includes the steps of forming a first conductive film on a gate oxide film in a MISFET forming region for a memory cell on a main surface of a semiconductor substrate, and forming a second conductive film via the gate oxide film to a thickness which is larger than the difference in a step between the first conductive film and the gate oxide film in a MISFET forming region for the peripheral circuit on the main surface of the semiconductor substrate, simultaneously with the formation of the second conductive film on the first conductive film in the MISFET forming region for the memory cell.

Abstract: A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminium film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.

Abstract: A protection circuit device for protecting a secondary battery from an overcharge and/or an overdischarge has first and second terminals, across which a charger and a load are alternatively connectable. A first switch and/or a second switch may be provided in series with the secondary battery between the first and second terminals. In a charging operation mode, the second switch is kept conductive. A charging operation is performed with the first switch made conductive. When the battery is overcharged for some reasons, the first switch is turned off. Upon connection of a load across the first and second terminals, the first switch is restored to a conductive state for a discharging operation which releases the battery from an overdischarge state. In a discharging operation mode, the first switch is kept conductive. A discharge operation is performed with the second switch made conductive.

Abstract: The resin-sealed package includes a lead frame having a supporting and heat spreading pad and inner and outer leads arranged to surround the supporting and head spreading pad. A tape automated bonding (TAB) structure is provided having a semiconductor chip having bonding pads formed on a periphery of a main surface of the semiconductor chip. A rear surface of the semiconductor chip is fixed to the supporting and head spreading pad. TAB leads are provided on the main surface of the semiconductor chip. One end of each TAB lead is connected with said bonding pads and the other end of each TAB lead is connected with one end of each inner lead of the lead frame. A resin molding is used for sealing the TAB structure and the supporting and head spreading pad and inner leads of the lead frame. An area of the supporting and head spreading pad is larger than that of the semiconductor chip of said TAB structure.

Abstract: A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.

Abstract: An information processing system has a processor, a first storage unit, a controller connected between said processor and said first storage unit, and a second storage unit connected to said processor and for storing dump data, and a dump method thereof are disclosed. The controller manages updated regions of the first storage unit as write regions. In response to a dump request issued by the processor, the controller manages regions which are managed as the write regions and included in a dump portion as protected regions. If a write request for a region which is managed as protected region, the controller saves contents of the region to dump point file before executing a write operation, and release the region from the protected regions. The controller transfers contents of regions managed as protected track and contents of the dump point file to the processor as contents of regions to be dumped.

Abstract: Part of a first signal path for amplifying a signal includes circuits for detecting a signal, and a second signal path connected to an input portion of the first signal path includes circuits for detecting the signal. A signal strength detector circuit adds outputs from the respective detector circuits in the first and second signal paths. The first signal path has a function of expanding the dynamic range in a smaller signal region as compared with the second signal path, while the second signal path has a function of expanding the dynamic range in a larger signal region as compared with the first signal path. When a radio transmitted output is variably controlled in a radio transmitter section based on a field strength detection output for a received signal, the transmitted output is optimized, resulting in minimizing consumed power and unnecessary radiation of radio waves.

Abstract: A graphics display system includes a host processor calculating graphic data and providing the graphic data to a graphics processor, and frame memories which store the graphic pixel data and supply display data to display devices. The graphics display system also includes a first register group which stores the graphics data, a second register group which converts and/or stores the data in the first register group, a pixel generator which generates pixels according to the graphic data in the second register group, and a plotter which writes the pixel data generated in the pixel generator in the frame memories. The second register group fetches the data from the first register group when the host processor issues a command for plotting, holds the data previously written by the host processor. At the same time, when the host processor issues a command for plotting, the specified graphic type is written in the graphic processor as sell as data calculated based on the first and second register groups.

Abstract: In order to improve the package body cracking resistance of an LSI package at the reflow soldering and to provide both a leadframe suitable for fabricating the LSI package according to the flexible manufacturing system and an LSI using the leadframe, the adhered area between a semiconductor chip 2 and a resin is enlarged by making the external size of a die pad 3 smaller than that of the semiconductor chip to be mounted thereon. Moreover, a variety of semiconductor chips 2 having different external sizes can be mounted on the die pad 3 by cutting the leading ends of leads 5 to a suitable length in accordance with the external sizes of the semiconductor chips 2.

Abstract: In allocating an area of a cache memory to each storage unit, proper allocation of the cache memory is made to each storage unit. If the amount of write-after data becomes equal to or more than a threshold value, an allocation limit is set to each disk unit. If CPU issues a data write request requiring the amount of data equal to or more than the allocation limit, the data write request is held in a wait state until the amount of write-after data becomes less than the allocation limit. Therefore, the allocation amount to the disk unit becomes neither too large nor too small. In this manner, proper allocation of the cache memory to each disk unit can be realized.

Abstract: A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.

Abstract: In an electronic device comprising a first substrate having at least one first electronic circuit element thereon, a second substrate having at least one second electronic circuit element thereon, a substrate connector through which the first and second electronic circuit elements are connected electrically to each other, and an electrically grounded chassis receiving the first and second substrates, the first substrate has thereon a first electromagnetic shielding plate including an electrically conductive material, the second substrate has thereon a second electromagnetic shielding plate including the electrically conductive material, the first and second electromagnetic shielding plates are electrically connected to the chassis, and a wire length between a wire length limited electronic circuit element on the first substrate and another of the electronic circuit elements on the second substrate is limited for ensuring a high speed responsive operation therebetween.

Abstract: Data communication method and system for transmitting a large amount of data via a network such as LAN to which a plurality of stations or terminals are connected, through a simplified processing procedure with high reliability and high efficiency while suppressing influence to other communications. The large amount of data is transmitted from a sender station to a plurality of receiver stations by utilizing a connectionless communication service, while inter-station reception acknowledging/retransmitting processings are performed by using a connection-oriented communication service. The large amount of data to be transmitted is divided into a plurality of blocks, and inter-block delay time is set on the basis of station status factors such as a permissible load increase rate of the CPU of the individual stations.

Abstract: A storage control unit is connected between a central processing unit having an interface for accessing a first disk unit into which data constructed of a plurality of variable length data records are stored in a first recording format, and a second disk unit into which data constructed of a plurality of fixed length data blocks are recorded in a second recording format. The storage control unit contains a plurality of first-level storage regions having a storage capacity equal to a track of the first disk unit, and the first-level storage regions have a plurality of cache memories constructed of a plurality of second-level storage regions having storage capacities equal to the fixed length blocks in the second recording format.