Abstract: A division method and circuit performs a division for signed data by adding or subtracting a divisor to or from the dividend or the partial remainder from the division, according to the sign of the divisor or the dividend and the partial remainder to acquire a new partial remainder. The division is repeated a predetermined number of times in which a quotient bit is acquired according to the sign of the acquired partial remainder or the divisor. The dividend is corrected by subtracting 1, which is the significance of an LSB of the corresponding dividend, from the dividend when the sign of the dividend is negative, and the corrected dividend is used for the division processing.

Abstract: A method of manufacturing a semiconductor integrated circuit device includes the steps of forming a first conductive film on a gate oxide film in a MISFET forming region for a memory cell on a main surface of a semiconductor substrate, and forming a second conductive film via the gate oxide film to a thickness which is larger than the difference in a step between the first conductive film and the gate oxide film in a MISFET forming region for the peripheral circuit on the main surface of the semiconductor substrate, simultaneously with the formation of the second conductive film on the first conductive film in the MISFET forming region for the memory cell.

Abstract: A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminium film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.

Abstract: A protection circuit device for protecting a secondary battery from an overcharge and/or an overdischarge has first and second terminals, across which a charger and a load are alternatively connectable. A first switch and/or a second switch may be provided in series with the secondary battery between the first and second terminals. In a charging operation mode, the second switch is kept conductive. A charging operation is performed with the first switch made conductive. When the battery is overcharged for some reasons, the first switch is turned off. Upon connection of a load across the first and second terminals, the first switch is restored to a conductive state for a discharging operation which releases the battery from an overdischarge state. In a discharging operation mode, the first switch is kept conductive. A discharge operation is performed with the second switch made conductive.

Abstract: The resin-sealed package includes a lead frame having a supporting and heat spreading pad and inner and outer leads arranged to surround the supporting and head spreading pad. A tape automated bonding (TAB) structure is provided having a semiconductor chip having bonding pads formed on a periphery of a main surface of the semiconductor chip. A rear surface of the semiconductor chip is fixed to the supporting and head spreading pad. TAB leads are provided on the main surface of the semiconductor chip. One end of each TAB lead is connected with said bonding pads and the other end of each TAB lead is connected with one end of each inner lead of the lead frame. A resin molding is used for sealing the TAB structure and the supporting and head spreading pad and inner leads of the lead frame. An area of the supporting and head spreading pad is larger than that of the semiconductor chip of said TAB structure.

Abstract: A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.

Abstract: A wireless LAN system which allows the transmission and reception of various data without lowering the transmission efficiency and the transmission quality even in an overlapping environment of areas of a plurality of wireless LANs and a base station apparatus therefor are provided. The wireless LAN system has a plurality of wireless LANs including base stations and wireless terminal devices, and the base stations and the wireless terminal devices in the wireless LANs communicate while sequentially hopping carrier frequencies to conduct the intercommunication between the base stations in the wireless LANs through inter-base station communication units.

Abstract: A document processing method and system for automizing extraction of source language sentences from figures, which is the pre-processing for figure translation, as well as embedding of translated sentences in drawings, which is the postprocessing in figure translation. The pre-processing consists of recognizing the regions included in a source figure, extracting a sentence from each region, and extracting the topological characteristics of the figure, and the post-processing consists of enlarging shrinking each sentence display region according to the change of the sentence length by translation, and generating a figure which preserves the extracted topological characteristics and includes the enlarged/shrinked sentence display regions.

Abstract: An information processing system has a processor, a first storage unit, a controller connected between said processor and said first storage unit, and a second storage unit connected to said processor and for storing dump data, and a dump method thereof are disclosed. The controller manages updated regions of the first storage unit as write regions. In response to a dump request issued by the processor, the controller manages regions which are managed as the write regions and included in a dump portion as protected regions. If a write request for a region which is managed as protected region, the controller saves contents of the region to dump point file before executing a write operation, and release the region from the protected regions. The controller transfers contents of regions managed as protected track and contents of the dump point file to the processor as contents of regions to be dumped.

Abstract: A phase lock loop system includes: a phase detecting circuit which operates on the basis of a signal waveform; a current output circuit for generating a current value from a phase difference detected by the phase detecting circuit; a filter which is constructed by only a resistor in a phase locked state by a synchronizing signal and by a capacitor and the resistor upon phase following state; and a voltage controlled oscillator for controlling an oscillation frequency by a voltage output of the filter. The phase lock loop system operates as a primary phase lock loop circuit in the phase locked state by the synchronizing signal and operates as a secondary phase lock loop circuit upon phase following state.

Abstract: A microcomputer that is easy to use and connected direct to such memories as dynamic and static RAM's and to other peripheral circuits. The microcomputer has strobe signal output terminals CASH*, CASL* and RAS* for direct connection to a dynamic RAM, and chip select signal output terminals CS0* through CS6* for outputting a chip select signal in parallel with the output from the strobe signal output terminals. The microcomputer further includes address output terminals for outputting a non-multiplexed or multiplexed address signal as needed, and data I/O terminals for selectively outputting the address signal to comply with a multiple-bus interface scheme.

Abstract: According to the present invention, the surface of the sample is cleaned with water immediately after ashing of the resist the quality of which has been changed through ion implantation by ozone-containing gas, or ozone-containing gas and ultraviolet ray, or the sample is cleaned with water without being exposed to the atmosphere after ashing, thereby allowing the number of residues to be reduced to 1/100, decreasing the load in cleaning process by solution, cutting down the semiconductor device production cost and improving the semiconductor device productivity.

Abstract: A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.

Abstract: Part of a first signal path for amplifying a signal includes circuits for detecting a signal, and a second signal path connected to an input portion of the first signal path includes circuits for detecting the signal. A signal strength detector circuit adds outputs from the respective detector circuits in the first and second signal paths. The first signal path has a function of expanding the dynamic range in a smaller signal region as compared with the second signal path, while the second signal path has a function of expanding the dynamic range in a larger signal region as compared with the first signal path. When a radio transmitted output is variably controlled in a radio transmitter section based on a field strength detection output for a received signal, the transmitted output is optimized, resulting in minimizing consumed power and unnecessary radiation of radio waves.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A graphics display system includes a host processor calculating graphic data and providing the graphic data to a graphics processor, and frame memories which store the graphic pixel data and supply display data to display devices. The graphics display system also includes a first register group which stores the graphics data, a second register group which converts and/or stores the data in the first register group, a pixel generator which generates pixels according to the graphic data in the second register group, and a plotter which writes the pixel data generated in the pixel generator in the frame memories. The second register group fetches the data from the first register group when the host processor issues a command for plotting, holds the data previously written by the host processor. At the same time, when the host processor issues a command for plotting, the specified graphic type is written in the graphic processor as sell as data calculated based on the first and second register groups.

Abstract: A disk array controller is connected to both a host computer and a plurality of disk drives operating in parallel. The disk array controller is responsive to an output request from the host computer for dividing data supplied from the host computer and parallel writing the divided data in the plurality of disk drives. In response to an input request from the host computer, the disk array controller combines data parallelly read from the disk drives into a set of data. Responsive to the output request, a processor stores in a non-volatile memory a write status of each block within a data write area for each disk drive to which data is to be written. The write status includes a first status representing a write completed status of each disk drive, a second status representing a writing status of each disk drive, and a third status representing a no write indication status of each disk drive.

Abstract: In order to improve the package body cracking resistance of an LSI package at the reflow soldering and to provide both a leadframe suitable for fabricating the LSI package according to the flexible manufacturing system and an LSI using the leadframe, the adhered area between a semiconductor chip 2 and a resin is enlarged by making the external size of a die pad 3 smaller than that of the semiconductor chip to be mounted thereon. Moreover, a variety of semiconductor chips 2 having different external sizes can be mounted on the die pad 3 by cutting the leading ends of leads 5 to a suitable length in accordance with the external sizes of the semiconductor chips 2.

Abstract: In allocating an area of a cache memory to each storage unit, proper allocation of the cache memory is made to each storage unit. If the amount of write-after data becomes equal to or more than a threshold value, an allocation limit is set to each disk unit. If CPU issues a data write request requiring the amount of data equal to or more than the allocation limit, the data write request is held in a wait state until the amount of write-after data becomes less than the allocation limit. Therefore, the allocation amount to the disk unit becomes neither too large nor too small. In this manner, proper allocation of the cache memory to each disk unit can be realized.

Abstract: An apparatus for reproducing recorded information reads information from the track surface of a CD-ROM disk 1, performs error detection and correction processing on the read information to reproduce recorded information and then outputs the reproduced information. This apparatus includes a control device 11, which switches a reproduction operation to the standard speed mode in response to a correction failure condition generated in the quadruple speed mode and retries standard-speed reading of the information read with an error uncorrectable in the quadruple speed mode. Reducing the signal read speed to one-fourth in the retry processing at the standard speed improves the C/N ratio of the high-frequency signal RF by 6 dB, which in turn improves the correction capability for random errors.