Abstract: A read-only memory has a terminal for receiving a writing current and a data input/output terminal. In the writing operation, the writing current is supplied to the terminal which is different from the data input/output terminal. Therefore, a data output circuit can be constituted by an ECL circuit having a relatively low withstand voltage, and a selection circuit related to the reading operation is achieved by using an ECL circuit. Accordingly, the read-only memory performs the reading operation at high speeds. During the writing operation, a different selection circuit is used which can withstand high voltages.

Abstract: A reliability analyzing system for manufacturing processes is disclosed, which comprises a computer system provided with a data memory device, a central processing device and input/output devices, terminals which input/output information into/from said computer system, and output devices for manufacturing sites; whereby said data memory device stores required specifications for each product, works for manufacturing and controlling processes, information relating to items, such as required specifications, works, control items, etc. and information mutually relating different items, and on the basis of the stored information, reliability analysis for each process is effected for all the processes and reliability analysis for each required specification is performed for all the required specifications.

Abstract: A sign generation system having a plurality of carry save adders. When adding a sum and a carry generated by a carry save adder in a next stage carry save adder, a full sum of two-bit sign fields adjacent to data fields of the sum and the carry is calculated.The resulting two-bit sign is combined with a constant to generate an exact sign, decreasing number of transferred sign bits.

Abstract: A protective cover for photoprinting system comprises a cover portion made of a transparent thin plate of inorganic material, an antireflection multiple coating provided on at least one of the inner and outer surfaces of the cover plate, and a spacer arranged on the peripheral portion of the cover plate for keeping the inner surface of the cover plate away from the surface to be protected, e.g., pattern surface of photomask and sealing the space between them.Since the cover plate is made of inorganic material, the mechanical strength thereof is large. Since the cover plate is thin and the antireflection multiple coating is provided on the cover plate, absorption of light therein is little and confusion of the pattern image due to rays reflected by the boundaries of the cover plate is ignorable.

Abstract: A nonvolatile memory which has both the merits of a floating gate type EEPROM and an MNOS type EEPROM and which can be written into and erased with low voltages is disclosed. Each memory element in the nonvolatile memory has a floating gate, a control gate, a gate insulator film between a semiconductor body and the floating gate, and an inter-layer insulator film between the control gate and the floating gate. The gate insulator film is made up of a very thin SiO.sub.2 film and a thin Si.sub.3 N.sub.4 film formed thereon. The charge centroid of charges injected for storing data lies within the floating gate, not within the Si.sub.3 N.sub.4 film.

Abstract: This invention discloses a semiconductor device, and method of manufacturing such device, which provides a high degree of moistureproofing, provides a high production yield, and in which defective elements can be replaced by the use of fuses. A circuit test of the device is conducted while at least part of each of a fuse and a bonding pad is exposed through a first passivation film covering a semiconductor substrate on which circuit elements such as MISFETs and capacitors are formed, and any defective elements are replaced by the use of fuses. Contamination of and damage to the elements during the test can thus be prevented. Thereafter, a second passivation film is formed so as to cover all the essential portions of the fuses and bonding pads. The exposure of cracks in the fuses and bonding pads is thus prevented, and the invasion of moisture, etc., into the lower layers below the fuses and bonding pads is also prevented, thereby improving the moistureproofing and reliability of the device.

Abstract: A memory device in accordance with the invention has an array of memory cells including a plurality of main memory cells which are adapted to be utilized by a user for storing information and a plurality of checking memory cells which store data placed therein at the time of manufacturing of the array which is read out to check a performance characteristic of the array of memory cells prior to the storing of data in the main memory cells. Addressing means are associated with the array of memory cells for permitting selective addressing of either the main memory cells or the checking memory cells within the array by the application of selected first or second signal levels to addressing lines coupled to the array. An output circuit is coupled to the array of memory cells for outputting data from within selected cells within the array in cooperation with the addressing circuit.

Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.

Abstract: A method of editing a document comprises displaying a text sentence on the screen of a display unit, bounding an area partly removed of the displayed text sentence and reserved for the display of a figure, calculating a configuration which the bounded area has on the document to be printed, displaying an area having a size in proportion to the configuration on the display screen, drawing the figure within the displayed area, and synthesizing the text sentence and the figure. When drawing the figure on the screen of the display unit, the user can monitor a print image.

Abstract: A frequency-voltage converter comprising a feedback frequency generating means associated with controlled means, a saw-tooth wave generating means, a current source for the saw-tooth wave, pulse generating means and sample-and-hold means, the frequency-voltage converter being characterized by further provision of supply voltage switching means for changing the feedback frequency of the controlled means by changing the voltage to be supplied to the current source to change the current from the current source and to thereby the slope of the saw-tooth wave from the saw-tooth wave generating means.

Abstract: YA semiconductor memory is provided with memory cells for storing a plurality of sets of data, each of the sets having check bits. A selecting circuit selects some of the memory cells to form a set in response to a first address signal. The circuit includes an error correcting code circuit, a tristate circuit and a control circuit which forms a control signal to control the tristate circuit. Output terminals of the tristate circuit are coupled with external output terminals of the semiconductor memory. Also, the tristate circuit is controlled by the control signal to bring the external circuit terminals into high impedance at least during the time when the error correcting code circuit is delivering indefinite data.

Abstract: The address of each defective memory cell in a memory cell array is stored within a semiconductor ROM in advance. In parallel with the operation of reading out information from a memory cell of the array, whether or not the address of the memory cell agrees with the previously stored address of a defective memory cell is distinguished. When they agree, a correcting signal is formed. Erroneous data read out from the defective memory cell is inverted on the basis of the correcting signal and thus corrected, whereupon the corrected data is delivered out of the ROM. In using this error data correcting system, a read-out access time delay caused by furnishing the correcting function corresponds to only one stage of a logic circuit which is used for the inversion to correct the erroneous data. Thus, a semiconductor ROM furnished with an error correcting function can be provided without spoiling enhancement in the speed of the read-out operation.

Abstract: An address multiplex type system for a dynamic RAM includes a memory cell array having a plurality of memory cells which are simultaneously selected by signals output from an address decoder, a decoder, and a shift register. The dynamic RAM further includes a selecting circuit which receives a plurality of address signals applied externally through one of a plurality of pins of a package in a time-sharing manner and makes it possible to write or read data into or from one memory cell of the plurality of memory cells selected. The dynamic RAM can read out or write in serially data of a plurality of memory cells selected from the memory cell array when a shift register operates. The dynamic RAM can also read or write data serially into or from a plurality of memory cells selected from the memory cell array simply by connecting the pin to a predetermined potential.

Abstract: An integrator circuit comprising reset means by which, when it is detected that an integrator output V.sub.p for an input analog signal coincides with a plus or minus reference value, the integral output is reset to the vicinity of the middle of the plus and minus reference values, in effect, without interrupting the integrating operation; a circuit which produces a pulse each time coincidence is detected; and a circuit which produces a direction signal indicating whether the coincidence results from an increase or a decrease of the integral input.The pulses produced in the state in which the direction signal is indicating an increase are counted up, and the pulses produced in the state in which the direction signal is indicating a decrease are counted down, whereby the precise integral value of the input analog signal can be detected.

Abstract: In a dynamic RAM having a memory array of a folded bit line arrangement, the memory array has a plurality of bit line pairs. A plurality of word lines and dummy word lines cross each of the bit line pairs so as to apply coupling noises of the same phase to the bit lines constituting each of the bit line pairs. The levels of the coupling noises applied to the bit lines constituting each of the bit line pairs, however, are also affected by the stray capacitance between the bit lines. Since the bit line disposed at an end part of the memory array has only one adjacent bit line disposed on one side thereof, only a relatively small stray capacitance is connected to the bit line. This causes the coupling noise between bit lines at the bit line disposed at an end part of the memory array to be different than the degree of coupling noise between other bit lines in the array.

Abstract: In a magnetic bubble memory device in which magnetic bubbles are propagated under influence of a rotating magnetic field, a method of controlling a stop operation of a rotating magnetic field in which magnetic field is caused to further rotate beyond the stop direction for a predetermined over-rotation angle and is then caused to return to the stop direction which is followed by the removal of the magnetic field, is presented. The over-rotation angle is in a range of 10 to 40 degrees. The invention is applicable whether bubble drive is performed using a drive current of triangular, square or trapezoidal waveform.

Abstract: A semiconductor device has a diffused layer of a first conductivity type which extends to a buried layer of a second conductivity type, formed in a manner to extend from a part of a surface of a semiconductor layer of the second conductivity type which is epitaxially grown on a semiconductor substrate of the first conductivity type through the buried layer of the second conductivity type. A semiconductor junction capacitance is formed of the diffused layer of the first conductivity type and the buried layer of the second conductivity type, and the concentration of an impurity to be introduced into the buried layer of the second conductivity type is controlled.

Abstract: A time constant circuit capable of switching the characteristic, which is realized by a combination of an equivalent resistor made up of a switched capacitor and an ordinary capacitor, comprises a capacitor of the switched capacitor or the time constant circuit connected in parallel to a series circuit including a switching device and an additional capacitor. The characteristic is switched by turning on and off the additional capacitor by the switching device. The direct connection of a plurality of equivalent resistors with a plurality of switched capacitors and ordinary capacitors makes up an equalizer. The capacitor making up a switched capacitor is connected with a switching device and an additional capacitor so that the frequency characteristic of the equalizer is switchable by turning on and off the switching device. Each of the capacitors making up the switched capacitors, the capacitors making up the time constant circuits and the additional capacitors has an end thereof grounded.

Abstract: An abnormal surge voltage such as frictional static electricity is often applied to the external terminals of a MOSIC. In the past, the output MOS transistor in the MOSIC during normal handling of the device frequently will have its gate insulating film broken down by the application of such an abnormal surge voltage to the drain thereof. In order to prevent the gate insulating film from being broken down, in this manner a resistor is connected between the gate of the output MOS transistor and a drive circuit for driving that output MOS transistor. This construction using a resistor is superior to the construction in which the voltage to be applied to the drain of the output MOS transistor is clamped by the use of suitable clamp means only because, with the resistor arrangement, the output characteristics of the MOSIC are not restricted.

Abstract: In a static type RAM, a sense amplifier includes first and second dissymmetric type differential amplifier circuits each of which has a pair of differential transistors and an active load circuit such as a current mirror circuit connected to the drains of the differential transistors. One of balanced signals delivered from a memory cell is supplied to the non-inverting input terminal of the first dissymmetric type differential amplifier circuit and the inverting input terminal of the second dissymmetric type differential amplifier circuit. The other of said balanced signals is applied to the remaining input terminals of the first and second dissymmetric type differential amplifier circuits. As a result, notwithstanding that balanced signals cannot be delivered from each dissymmetric type differential amplifier circuit, amplified balanced signals can be obtained.