Abstract: A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.

Abstract: In an electronic device comprising a first substrate having at least one first electronic circuit element thereon, a second substrate having at least one second electronic circuit element thereon, a substrate connector through which the first and second electronic circuit elements are connected electrically to each other, and an electrically grounded chassis receiving the first and second substrates, the first substrate has thereon a first electromagnetic shielding plate including an electrically conductive material, the second substrate has thereon a second electromagnetic shielding plate including the electrically conductive material, the first and second electromagnetic shielding plates are electrically connected to the chassis, and a wire length between a wire length limited electronic circuit element on the first substrate and another of the electronic circuit elements on the second substrate is limited for ensuring a high speed responsive operation therebetween.

Abstract: Data communication method and system for transmitting a large amount of data via a network such as LAN to which a plurality of stations or terminals are connected, through a simplified processing procedure with high reliability and high efficiency while suppressing influence to other communications. The large amount of data is transmitted from a sender station to a plurality of receiver stations by utilizing a connectionless communication service, while inter-station reception acknowledging/retransmitting processings are performed by using a connection-oriented communication service. The large amount of data to be transmitted is divided into a plurality of blocks, and inter-block delay time is set on the basis of station status factors such as a permissible load increase rate of the CPU of the individual stations.

Abstract: A storage control unit is connected between a central processing unit having an interface for accessing a first disk unit into which data constructed of a plurality of variable length data records are stored in a first recording format, and a second disk unit into which data constructed of a plurality of fixed length data blocks are recorded in a second recording format. The storage control unit contains a plurality of first-level storage regions having a storage capacity equal to a track of the first disk unit, and the first-level storage regions have a plurality of cache memories constructed of a plurality of second-level storage regions having storage capacities equal to the fixed length blocks in the second recording format.

Abstract: The semiconductor integrated circuit device incorporates a power supply circuit which forms an operation voltage that matches the operation speed of the internal circuit. Since the operation voltage is set in accordance with the operation speed required of the internal circuit, the internal circuit can be operated with a minimum required voltage even when there are process variations and temperature changes. In other words, a rational power supply is realized.

Abstract: A microprocessor having a buffer or memory capable of holding a plurality of instructions in advance of execution also functions to insert a special bus cycle amongst the instructions for outputting the internal information of the microprocessor to the outside in a predetermined operation mode at the time of each execution. The information inside of the microprocessor, which is to be outputted to the outside in the special bus cycle, is identified by the address of the executed instruction in a memory space, an instruction code or the code for identifying said executed instruction in the instruction group prefetched. In an emulation of the system using the instruction prefetch type microprocessor, as described above, what instruction has been executed can be easily known from the outside to effect an accurate emulation analysis and to facilitate the analysis of trace data thereby to improve debugging efficiency.

Abstract: Block data of logical inconsistency stored in a disk array is inhibited to be transferred to a host computer, by detecting a range where data was written defectively because of a power cut or the like. A processor of a disk array controller allocates a write control table within a non-volatile memory when writing data to a drive group. The write status of each disk drive in each block is supervised by a write status flag. The write statuses include a no write indication status, a writing status, and a write completed status. If all the write statuses of the same block are the write completed status or no write indication status, data is transferred to the host computer. If all the data write statuses of the same block are neither the write completed status nor no write indication status, a read error is informed to the host computer.

Abstract: In a software distributedly preparing method for preparing a plurality of program modules combined by exchange of message data, in generating software modules and message data, repetition or similarity in the defined contents of the message data and multiple definition of a data item constituting the message data, and the defined contents of the message data are unified or separated to assure its consistency and preparing it as a data base which will be used in preparing a software module.

Abstract: A first reproduced color under signal is delayed by one or two horizontal periods by a delay circuit, and this delayed second reproduced color under signal and the aforementioned first reproduced color under signal have their frequencies converted individually by first and second frequency converters into standard color signals. An oscillatory frequency signals of 2n of carriers for the aforementioned frequency conversions are divided to have the aforementioned carrier frequencies and to produce four carriers having phases of 0, 90, 180 and 270 degrees. These carriers are selectively fed to the first and second frequency converters by switches so that the two frequency-converted signals are subtracted or added in phase or in opposite phase to clear the noise (or crosstalk component), which is caused by the crosstalk between the tracks.

Abstract: A subscriber terminal service system, which has a switchboard connected to a plurality of subscriber terminals and a computer connected with the switchboard and executes services to subscribers, has the functions of setting a flag indicative of the possibility/impossibility of the execution of an application on the basis of a message sent from the computer, referring to the flag in response to a service request sent from the subscriber terminal to determine whether or not the execution of the requested application should be permitted, sending a control message to the switchboard when the condition of possibility/impossibility of the execution of an application on the computer, and changing the content of the flag in the switchboard on the basis of the control message. The start or stop of any application executed in the computer is made through a console device connected with the computer or by a scheduler provided in the computer.

Abstract: In a communications system having a plurality of stations interconnected by a two-line circuit, in which the two-line circuit consists of a data bus circuit for transmitting a series of data bits between at least one sending station and at least one receiving station of the plurality of stations and a clock bus circuit for transmitting clock signals in synchronism with each of the data bits; the data bus circuit sends a signal or a command requesting the receiving station to enter a standby or an execute state after taking in data supplied, while a logic value on the clock bus circuit is fixed. In more detail, the sending station transmits signals to make at least one of the receiving stations enter the standby state after taking in data and then sends data to another receiving station, after which the sending station sends a signal or command to make both the first and second receiving stations simultaneously enter the execute state.

Abstract: A logic block of a memory (LSI) with logic functions includes RAM macrocells (RAMO-RAM7) and a centrally located gate array (GAO-GA5). Clock pulse shaping circuits (CSPO, CSP1) and input/output portion (I/O) surround the logic block. The logic block power supply includes a smoothing capacitor (CC) that is substantially the same size as a cell (GC) of the gate array. Each RAM macrocell has memory mats (MATOO-MAT21), word lines (WO-W127), data lines (DO-D7), and peripheral circuits (MPCOO-MPC21), which includes an address decoder and a sense amp (SAO). An input unit cell (ICO) receives ECL level signals and outputs ECL level signals (FIG. 5 ) and MOS level signals (FIG. 6 ). The input unit cells and analogous output unit cells (OCO) are selectively used singly or in parallel to accommodate signals of different form and driving capability. A wiring line replacement region (LRP) connects memory macrocell wiring lines with logic block wiring lines.

Abstract: Under such a condition between outputs of AND circuits for outputting All "0" when one of zero detecting circuits of two register identifiers within an instruction register detects "0", instead of a content of a general-purpose register designated by these identifiers, and also a carry derived from a page offset corresponding to an intermediate result of an address adder, when a page address portion of a logical address is known before this logical address is defined, selecting circuits are controlled, and then the address controller is bypassed to retrieve a translation look-aside buffer, thereby defining a real address. In case that the page address portion of the logical address register is identical to the page address portion of the base register, the translation look-aside buffer is previously retrieved in accordance with either the content of the index register, or the content of the base register so that the real address can be defined.

Abstract: A computer system has a plurality of processors, each having a local memory. An expression is represented by operands and operations and is expressed in a form of a tree. The operands are assigned to leaf nodes of the tree and the operations are assigned to interior nodes. Processors which store an operand represented by a leaf node are assigned to the leaf node. The tree is traced in a bottom-up fashion to determine a set of candidate processors to be assigned to each of the interior nodes. The candidate processors are determined from processors which are assigned to children nodes of each interior node in accordance with a majority method. The majority method is based on a rule that a processor which is most frequently assigned to the children nodes of an interior node is determined as a candidate processor. A root processor is assigned to a root node of the interior nodes from the candidate processors.

Abstract: In a multi-processor system having a plurality of processors connected to each other through a network, a method of executing a program under various environments, includes the steps of transmitting the program from a first processor to a second processor, the first and second processors being included in the plurality of processors, autonomously checking by the second processor whether or not an executing environment set in the program matches to an actual executing environment, autonomously changing the program by the second processor in accordance with the checking result, and executing the changed program by the second processor.

Abstract: A route information input apparatus for specifying a route from an entraining station to an arrival station including a pointing device operated by the user to designate a position on a display screen and a data processing apparatus for executing a data processing in accordance with a program prepared in advance each time the user operates the pointing device to thereby change a displayed content on the display screen. On the basis of positional informations of major stations stored in a first file, a line diagram presented in the simplified form in which truly existing stations are partly omitted and in which the major stations are connected by means of line segments is displayed on a first area of the display screen. A group of station name data omitted from the line diagram displayed on the first area are selectively displayed on a second area of the display screen in the form of a table.

Abstract: A method and apparatus for controlling a conditional branch instruction in a pipeline type data processing apparatus which are adapted to judge whether or not a conditional branch instruction is valid, judge whether or not a condition code necessary for a taken/not-taken judgement made for the conditional branch instruction is valid, and selectively make a taken/not-taken judgement for the conditional branch instruction in accordance with the results of the judgements made to the conditional branch instruction and the condition code.

Abstract: A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.

Abstract: An information processing apparatus employs a liquid crystal display and a fluorescent lamp for backlighting the screen of the liquid crystal display. A lighting circuit for supplying alternating current lighting power to the fluorescent lamp receives input power from either a commercial alternating current power source or from a direct current battery. The level of the lighting power supplied to the fluorescent lamp is determined based upon a determination of whether the input power is being supplied from the commercial power source or from the battery.

Abstract: In order to improve the package body cracking resistance of an LSI package at the reflow soldering and to provide both a leadframe suitable for fabricating the LSI package according to the flexible manufacturing system and an LSI using the leadframe, the adhered area between a semiconductor chip 2 and a resin is enlarged by making the external size of a die pad 3 smaller than that of the semiconductor chip to be mounted thereon. Moreover, a variety of semiconductor chips 2 having different external sizes can be mounted on the die pad 3 by cutting the leading ends of leads 5 to a suitable length in accordance with the external sizes of the semiconductor chips 2.