Patents Assigned to Hitachi Process Computer Engineering, Inc.
  • Patent number: 6975648
    Abstract: A network system has a plurality of nodes being operated by their communication application programs. In the network system, each of the nodes includes a transmission rate control module for obtaining a communication attribute required for controlling a communication band from the communication application program, a band information managing table for storing the obtained communication attribute, a band information transmitting module for delivering the band information of the local node to all the other nodes connected with the network, a band information receiving module for receiving the band information delivered by the band information transmitting module of another node and storing the band information in the band information managing table. The transmission rate control module is served to obtain the current band traffic on the basis of the band information stored in the band information managing table and perform the band control.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: December 13, 2005
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Hisao Kikuchi, Atsushi Matsuno, Kiyokazu Tamura, Yoshiaki Adachi, Hideki Tonooka
  • Patent number: 6879358
    Abstract: A liquid crystal light valve includes a semiconductor substrate having a region for a plurality of switching elements formed in a matrix form. A first metal layer is formed on the surface of the semiconductor substrate through an insulating layer and divided into a plurality of parts by first slits. A second metal layer is formed on the first metal layer through another insulating layer and divided into a plurality of parts by second slits. A third metal layer is formed on the second metal layer through still another insulating layer and divided into a plurality of parts by third slits. An opposite substrate has an opposite electrode on a surface thereof, disposed so as to be opposite to said third metal layer through an interval on the opposite electrode side. Liquid crystal fills the interval between said opposite electrode and the third metal layer.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: April 12, 2005
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Hideo Sato, Minoru Hoshino, Yuji Mori, Shinichi Komura, Yoshiharu Nagae, Ichirou Katsuyama, Tetsuya Nagata, Akira Arimoto, Akio Hayasaka
  • Patent number: 6693691
    Abstract: A liquid crystal light valve includes a semiconductor substrate having a region for a plurality of switching elements formed in a matrix form. A first metal layer is formed on the surface of the semiconductor substrate through an insulating layer and divided into a plurality of parts by first slits. A second metal layer is formed on the first metal layer through another insulating layer and divided into a plurality of parts by second slits. A third metal layer is formed on the second metal layer through still another insulating layer and divided into a plurality of parts by third slits. An opposite substrate has an opposite electrode on a surface thereof, disposed so as to be opposite to said third metal layer through an interval on the opposite electrode side. Liquid crystal fills the interval between said opposite electrode and the third metal layer.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: February 17, 2004
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Hideo Sato, Minoru Hoshino, Yuji Mori, Shinichi Komura, Yoshiharu Nagae, Ichirou Katsuyama, Tetsuya Nagata, Akira Arimoto, Akio Hayasaka
  • Patent number: 6686976
    Abstract: A liquid crystal light valve includes a semiconductor substrate having a region for a plurality of switching elements formed in a matrix form. A first metal layer is formed on the surface of the semi-conductor substrate through an insulating layer and divided into a plurality of parts by first slits. A second metal layer is formed on the first metal layer through another insulating layer and divided into a plurality of parts by second slits. A third metal layer is formed on the second metal layer through still another insulating layer and divided into a plurality of parts by third slits. An opposite substrate has an opposite electrode on a surface thereof, disposed so as to be opposite to said third metal layer through an interval on the opposite electrode side. Liquid crystal fills the interval between said opposite electrode and the third metal layer.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: February 3, 2004
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Hideo Sato, Minoru Hoshino, Yuji Mori, Shinichi Komura, Yoshiharu Nagae, Ichirou Katsuyama, Tetsuya Nagata, Akira Arimoto, Akio Hayasaka
  • Patent number: 6437842
    Abstract: A liquid crystal light valve includes a semiconductor substrate having a region for a plurality of switching elements formed in a matrix form. A first metal layer is formed on the surface of the semi-conductor substrate through an insulating layer and divided into a plurality of parts by first slits. A second metal layer is formed on the first metal layer through another insulating layer and divided into a plurality of parts by second slits. A third metal layer is formed on the second metal layer through still another insulating layer and divided into a plurality of parts by third slits. An opposite substrate has an opposite electrode on a surface thereof, disposed so as to be opposite to said third metal layer through an interval on the opposite electrode side. Liquid crystal fills the interval between said opposite electrode and the third metal layer.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: August 20, 2002
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Hideo Sato, Minoru Hoshino, Yuji Mori, Shinichi Komura, Yoshiharu Nagae, Ichirou Katsuyama, Tetsuya Nagata, Akira Arimoto, Akio Hayasaka
  • Patent number: 6216236
    Abstract: A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20-2, 20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2-2, 2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails.
    Type: Grant
    Filed: November 10, 1998
    Date of Patent: April 10, 2001
    Assignees: Tokyo, Japan, Hitachi Process Computer Engineering, Inc.
    Inventors: Takeshi Miyao, Manabu Araoka, Tomoaki Nakamura, Masayuki Tanji, Shigenori Kaneko, Koji Masui, Saburou Iijima, Nobuyasu Kanekawa, Shinichiro Kanekawa, Yoshiki Kobayashi, Hiroaki Fukumaru, Katsunori Tagiri
  • Patent number: 5901281
    Abstract: A computer system has a plurality of processing units connected via one or more system buses. Each processing unit has three or more processors on a common support board (PL) and controlled by a common clock unit. The three processors perform the same operation and a fault in a processor is detected by comparison of the operations of the three processors. If one processor fails, the operation can continue in the other two processors of the processing unit, at least temporarily, before replacement of the entire processing unit. Furthermore, the processing unit may have a plurality of clocks (A,B) within the clock unit, with a switching arrangement so that the processors normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B).
    Type: Grant
    Filed: May 3, 1995
    Date of Patent: May 4, 1999
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Takeshi Miyao, Manabu Araoka, Tomoaki Nakamura, Masayuki Tanji, Shigenori Kaneko, Koji Masui, Saburou Iijima, Nobuyasu Kanekawa, Shinichiro Kanekawa, Yoshiki Kobayashi, Hiroaki Fukumaru, Katsunori Tagiri
  • Patent number: 5890220
    Abstract: In a computer system having an address converter for DMA (direct memory access), an address conversion apparatus in which a memory area to be accessed by the DMA can be accessed at high speed from a CPU. A "DMA address conversion area" is defined in a memory space, and address conversion means in the mode of accessing the DMA address conversion area is so constructed that, when the area has been accessed from the CPU, a physical address is generated in accordance with the address conversion routine of the DMA address conversion means or converter, so as to access a main storage. The memory area to be accessed by the DMA can be quickly accessed from the CPU without requiring such an operation as especially accessing the control ware of the address converter or producing the physical address under the management of a program run on the CPU.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: March 30, 1999
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Tetsuya Mochida, Hitoshi Kawaguchi, Kazushi Kobayashi, Ichiharu Aburano, Takanori Ishikawa
  • Patent number: 5787464
    Abstract: A computer system and method for enabling memory expansion without shutting off the computer system are disclosed. The computer system has a dual memory configuration and supports memory insertion and extraction while being on-line. The memory content of one system may be copied to the memory of another system according to a predetermined priority or after a predetermined delay. Memory may be used efficiently during the insertion or extraction by securing a status management table expansion area in an expanded portion of memory. Memory may be expanded in computer systems that do not have an open memory slot by replacing the installed memory with a memory having a larger capacity.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: July 28, 1998
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Ryokichi Yoshizawa, Takeshi Miyao, Shigenori Kaneko, Tomoaki Nakamura, Hidebumi Miyata
  • Patent number: 5740424
    Abstract: There is disclosed an information processing system and method capable of coping with a wider range of subjects and intricate changes. In client server structure, time-varying database altering information received from external systems is pooled in servers and distributed to a number of distributed terminals or clients, using broadcasting communication.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: April 14, 1998
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering Inc.
    Inventors: Hiroshi Wataya, Hiroaki Nakanishi, Keijiro Hayashi, Yoshiaki Adachi, Hideki Tonooka, Kenji Matsuzaki, Tsutomu Onuki, Isao Terakado
  • Patent number: 5706422
    Abstract: A plurality of different fault locating functions are provided in a communication system comprising a plurality of terminals connected to a data transmission channel. The functions are at different levels, respectively, ranging from a level for rapid fault location to a level for reliable and sure fault location. Upon detection of an occurrence of a fault, one fault locating function is performed. If the fault is not located accurately located, another fault locating function of a level for more reliable is performed, thus the functions are performed sequentially in the order from the level for rapid location to the level for more deliberate and reliable location. Preferably, the channel is reconfigured to avoid the fault, according to the fault located by the functions of the respective levels. With this arrangement, a fault which does most possibly occur can be located quickly, while another fault difficult to locate can be located accurately.
    Type: Grant
    Filed: July 16, 1996
    Date of Patent: January 6, 1998
    Assignees: Hitachi Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Hisayuki Maruyama, Jushi Ide, Seiichi Yasumoto, Sadao Mizokawa, Ken Onuki, Toshio Ishihara, Masato Satake, Toshihiko Uchiyama
  • Patent number: 5651112
    Abstract: An information processing system capable of performance measurement by the use of a small amount of mounted hardware. The information processing system having central processors installed therein comprises a control circuit, and a performance measurement validation register for specifying whether a performance measurement function is valid or invalid. In a case where the validity of the measurement function has been specified by the register, the control circuit operates one loop in a duplex configuration as a performance measurement facility. At this time, counter #1-counter #3 are used as counters for totalizing performance information. On the other hand, in a case where the invalidity of the measurement function has been specified, both loops in the duplex configuration are operated as the central processors. At this time, the counter #1-the counter #3 are used as timer counters for controlling buses.
    Type: Grant
    Filed: February 22, 1996
    Date of Patent: July 22, 1997
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Atsushi Matsuno, Masanori Naito, Hiroshi Kobayashi, Masanori Horie, Hideki Sato, Masayuki Tanji, Shigeaki Wada, Toshimasa Saika
  • Patent number: 5585821
    Abstract: An apparatus and a method of screen display whereby either a plurality of screens or a plurality of windows on a single screen are displayed. On at least one screen or in at least one window, areas representing either the other screens or the other windows are displayed. When a pointer pointing to a given position either on that one screen or in that one window is used to select any one of these areas therein, the pointer is made to appear either on another screen or in another window corresponding to the selected area.
    Type: Grant
    Filed: December 20, 1995
    Date of Patent: December 17, 1996
    Assignees: Hitachi Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Shuji Ishikura, Takayuki Morioka, Atsuhiko Nishikawa, Kayo Takahashi, Norihito Kanno
  • Patent number: 5497374
    Abstract: A data transmission method and system of a token passing type capable of periodically transmitting cyclic data produced in a station to other stations while enabling a packet data communication with high efficiency and without disturbing the periodicity of the cyclic communication. A token circulation time is set to be shorter than a cycle time for production of the cyclic data where no packet data to be transmitted. Also each station will pass an acquired token immediately to the next station if the station has no data to be transmitted. Thus, at least one station can have a token at least two times during the cycle time to transmit the cyclic data and the packet data. Upper limits may be set to capacities of the cyclic data and the packet data which are capable of being transmitted each time the token is acquired.
    Type: Grant
    Filed: September 2, 1994
    Date of Patent: March 5, 1996
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Hisayuki Maruyama, Sadao Mizokawa, Seiichi Yasumoto, Ken Onuki, Hisao Ogawa, Junji Fukuzawa, Toshihiko Uchiyama, Toshiyuki Murakami, Osamu Anbo, Masato Satake
  • Patent number: 5461501
    Abstract: A liquid crystal light valve includes a semiconductor substrate having a region for a plurality of switching elements formed in a matrix form. A first metal layer is formed on the surface of the semiconductor substrate through an insulating layer and divided into a plurality of parts by first slits. A second metal layer is formed on the first metal layer through another insulating layer and divided into a plurality of parts by second slits. A third metal layer is formed on the second metal layer through still another insulating layer and divided into a plurality of parts by third slits. An opposite substrate has an opposite electrode on a surface thereof, disposed so as to be opposite to said third metal layer through an interval on the opposite electrode side. Liquid crystal fills the interval between said opposite electrode and the third metal layer.
    Type: Grant
    Filed: October 6, 1993
    Date of Patent: October 24, 1995
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Hideo Sato, Minoru Hoshino, Yuji Mori, Shinichi Komura, Yoshiharu Nagae, Ichirou Katsuyama, Tetsuya Nagata, Akira Arimoto, Akio Hayasaka
  • Patent number: 5432715
    Abstract: A computer system and monitoring method for efficiently monitoring a plurality of computers interconnected within a network. In this computer network system, each computer has a self-monitoring unit for monitoring its own computer and acquiring a monitor message, and a transmitting unit for transmitting the monitor message to a monitoring computer. Monitor messages transmitted from a plurality of computers are received by the monitoring computer. The monitoring computer has a receiving unit for receiving monitor messages, and a displaying unit for outputting monitor messages to a display. The receiving unit, displaying unit, and display windows on the display are provided for each of a plurality of computers to be monitored.
    Type: Grant
    Filed: June 29, 1993
    Date of Patent: July 11, 1995
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Mari Shigematsu, Teruyasu Nakahashi, Hideki Sato, Keiichi Sannomiya, Kouji Kobayashi, Kazuma Nakao, Hajime Fujimoto, Yasushi Kobayashi
  • Patent number: 5426638
    Abstract: A data transmission method and system of a token passing type capable of periodically transmitting cyclic data produced in a station to other stations while enabling a packet data communication with high efficiency and without disturbing the periodicity of the cyclic communication. A token circulation time is set to be shorter than a cycle time for production of the cyclic data where no packet data is to be transmitted. Also each station will pass an acquired token immediately to the next station if the station has no data to be transmitted. Thus, at least one station can receives a token at least two times during the cycle time to transmit the cyclic data and the packet data. Upper limits may be set to capacities of the cyclic data and the packet data which are capable of being transmitted each time the token is acquired.
    Type: Grant
    Filed: March 19, 1990
    Date of Patent: June 20, 1995
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Hisayuki Maruyama, Sadao Mizokawa, Seiichi Yasumoto, Ken Onuki, Hisao Ogawa, Junji Fukuzawa, Toshihiko Uchiyama, Toshiyuki Murakami, Osamu Anbo, Masato Satake
  • Patent number: 5418404
    Abstract: In a data processing device, when exchanging a plug-in package with another without breaking the power to be supplied to the data processing device, a package removing lever is equipped with a locking piece. The lever does not move and the package hence cannot be removed, until the locking piece is released. In response to the release operation of the locking piece, a switch is activated to break off the power supply for the package. After the package is mounted perfectly, the power for the package is switched on by the action of the locking piece, thus preventing any misoperation when removing the package.
    Type: Grant
    Filed: June 14, 1994
    Date of Patent: May 23, 1995
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Manabu Araoka, Yoshiaki Takahashi, Atsushi Shikama, Yoshihiro Miyazaki, Tomoaki Nakamura, Masayuki Sakata
  • Patent number: 5396485
    Abstract: In an information communication system for performing both point-to-point communication and point-to-multipoint communication between a host computer and terminals by using same lines while distributing loads of data communication, data communication report tables are provided on a main storage unit of the host computer for each type of communication. The data communication process is executed distributively at each CPU unit and communication interface unit of the host computer and at each control module of a communication control unit. A plurality of destination pattern tables indicating data destinations are provided for point-to-multipoint communication. For the point-to-multipoint communication, CPU unit designates a particular destination pattern table for each interface unit, and data transmission is requested to each control module in accordance with the destination pattern table.
    Type: Grant
    Filed: August 24, 1993
    Date of Patent: March 7, 1995
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Shuji Ohno, Tetsuya Kawahara, Keiichi Nakane, Masakazu Okada, Syoji Yamaguchi, Yoshimi Fujimata
  • Patent number: 5343009
    Abstract: In a data processing device, when exchanging a plug-in package with another without breaking off the power to be supplied to the data processing device, a package removing lever is equipped with a locking piece. The lever does not move and the package hence cannot be removed, until the locking piece is released. In response to the release operation of the locking piece, a switch is activated to break off the power supply for the package. After the package is mounted perfectly, the power for the package is switched on by the action of the locking piece, thus preventing any misoperation when removing the package.
    Type: Grant
    Filed: December 17, 1991
    Date of Patent: August 30, 1994
    Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.
    Inventors: Manabu Araoka, Yoshiaki Takahashi, Atsushi Shikama, Yoshihiro Miyazaki, Tomoaki Nakamura, Masayuki Sakata