Patents Assigned to Hitachi Tobu Semiconductor Ltd.
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Publication number: 20130137223Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: ApplicationFiled: January 23, 2013Publication date: May 30, 2013Applicants: Hitachi Tobu Semiconductor, Ltd., Renesas Electronics CorporationInventors: Renesas Electronics Corporation, Hitachi Tobu Semiconductor, Ltd.
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Patent number: 8377775Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: February 15, 2012Date of Patent: February 19, 2013Assignees: Renesas Electronics Corporation, Hitachi Tobu Semiconductor, Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Patent number: 8278708Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: February 15, 2012Date of Patent: October 2, 2012Assignees: Renesas Electronics Corporation, Hitachi Tobu Semiconductor Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Publication number: 20120139040Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: ApplicationFiled: February 15, 2012Publication date: June 7, 2012Applicants: Hitachi Tobu Semiconductor, Ltd., Renesas Electronics CorporationInventors: HIROSHI INAGAWA, Nobuo Machida, Kentaro Oishi
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Publication number: 20120142156Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: ApplicationFiled: February 15, 2012Publication date: June 7, 2012Applicants: Hitachi Tobu Semiconductor, Ltd., Renesas Electronics CorporationInventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Patent number: 8168498Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: December 7, 2010Date of Patent: May 1, 2012Assignees: Renesas Electronics Corporation, Hitachi Tobu Semiconductor, Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Patent number: 8148224Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: September 23, 2011Date of Patent: April 3, 2012Assignees: Renesas Electronics Corporation, Hitachi Tobu Semiconductor, Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Publication number: 20120015492Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: ApplicationFiled: September 23, 2011Publication date: January 19, 2012Applicants: Hitachi Tobu Semiconductor, Ltd., Renesas Electronics CorporationInventors: HIROSHI INAGAWA, Nobuo Machida, Kentaro Oishi
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Publication number: 20110076818Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: ApplicationFiled: December 7, 2010Publication date: March 31, 2011Applicants: Renesas Electronics Corporation, Hitachi Tobu Semiconductor, Ltd.Inventors: HIROSHI INAGAWA, Nobuo Machida, Kentaro Oishi
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Patent number: 7910990Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: August 25, 2010Date of Patent: March 22, 2011Assignees: Renesas Electronics Corporation, Hitachi Tobu Semiconductor, Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Publication number: 20100320533Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: ApplicationFiled: August 25, 2010Publication date: December 23, 2010Applicants: Renesas Electronics Corporation, Hitachi Tobu Semiconductor, Ltd.Inventors: HIROSHI INAGAWA, Nobuo Machida, Kentaro Oishi
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Patent number: 7843001Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: August 11, 2009Date of Patent: November 30, 2010Assignees: Renesas Electronics Corporation, Hitachi Tobu Semiconductor Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Publication number: 20090294845Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: ApplicationFiled: August 11, 2009Publication date: December 3, 2009Applicants: Renesas Technology Corp., Hitachi Tobu Semiconductor, Ltd.Inventors: HIROSHI INAGAWA, Nobuo Machida, Kentaro Oishi
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Patent number: 7585732Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: February 26, 2008Date of Patent: September 8, 2009Assignees: Renesas Technology Corp., Hitachi Tobu Semiconductor, Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Publication number: 20080153235Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: ApplicationFiled: February 26, 2008Publication date: June 26, 2008Applicants: Renesas Technology Corp., Hitachi Tobu Semiconductor, Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Patent number: 7361557Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: January 16, 2007Date of Patent: April 22, 2008Assignees: Renesas Technology Corp., Hitachi Tobu Semiconductor Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Patent number: 7172941Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: November 10, 2004Date of Patent: February 6, 2007Assignees: Renesas Technology Corp., Hitachi Tobu Semiconductor Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Patent number: 6858896Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: January 16, 2002Date of Patent: February 22, 2005Assignees: Renesas Technology Corp., Hitachi Tobu Semiconductor Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Patent number: 6787374Abstract: A sorting section can be supplied with parts from plurality of supply sources. A semiconductor device sorting system is provided with a sorting section for sorting good transistors by means of an electric performance test thereof and supply sections adapted to separate the transistor parts that are collectively supplied in a complex into transistors and supply the separated transistors to the sorting section. An appropriate one of the supply sections can be selected corresponding to the supply form of the transistor parts to be separated. A selected supply section can be switched to another depending on the supply form of the transistor parts.Type: GrantFiled: February 27, 2002Date of Patent: September 7, 2004Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd.Inventors: Hisao Yamagata, Katsumi Oya
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Patent number: 6709890Abstract: In a method of manufacturing a high frequency module to be assembled by providing, on a wiring board, a chip part and a semiconductor pellet to be bare chip mounted and then mounting the chip part and the semiconductor pellet through soldering, the wiring board is separated from a heat block with the semiconductor pellet pressurized against the wiring board in a main heating portion heating and melting a reflow solder, thereby cooling a soldering portion. Consequently, the generation of a void in the soldering portion can be prevented and the connecting reliability of the soldering portion can be enhanced. In addition, a degree of mounting horizontality of the semiconductor pellet on the wiring board can be enhanced.Type: GrantFiled: February 15, 2001Date of Patent: March 23, 2004Assignees: Renesas Technology Corporation, Hitachi Tobu Semiconductor Ltd.Inventors: Tsutomu Ida, Akio Ishizu, Masakazu Hashizume, Isao Hagiwara, Yoshinori Shiokawa