Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.

Abstract: A non-volatile memory, an SRAM, a DRAM and a control circuit are module-formed into a single packaged. The control circuit assigns addresses to the SRAM and addresses to the DRAM and data necessary to be held for a long period of time is saved in the SRAM. Two chips of DRAM are mapped to the same address space and refreshed alternately. The plural chips are arranged such that they are mutually laminated, and they are wired by means of a BGA or inter-chip bonding.

Abstract: The configuration of a microcomputer to be used as the control device of a medium reading apparatus is such that writing unit by unit into and erasion block by block from a prescribed area, such as a user data storage area, in a nonvolatile memory built into the microcomputer makes possible, if any writing into the user data storage area is needed, for data to be successively written while updating the units, data included in the prescribed area to be erased when all the units have been written into, and the next data to be written into the erased blocks.

Abstract: A column select line YS1 can be enabled at the same time as the enabling of a word line. Write data is written from an I/O gate into a selected data line. An adjacent unselected sense amplifier reads data from memory cells. A source node of a cross-coupled sense amplifier connected to each data line pair is divided for each column select line, thereby to prevent a write-selected cross-coupled amplifier from driving the source node. In the write operation, data can be written at a high speed. On the other hand, it becomes possible to prevent a write-sense amplifier from driving the source node. Therefore, adjacent sense amplifiers can achieve stable read operation without being affected from the write-sense amplifier.

Abstract: A contact collect is provided to prevent damage to the top surface of a semiconductor chip at the time of die bonding the semiconductor chip. A protection tape is pasted to the top surface of the semiconductor chip before die bonding of the semiconductor chip is executed by pressing the back surface (underside) of the semiconductor chip sucked and securely held by the contact collect against respective chip-mounting regions of a multi-wiring board. The contact collect is, for example, substantially cylidrical in outside shape, and a bottom part (suction head) thereof is made of soft synthetic rubber, etc. The protection tape pasted to the top surface of the semiconductor chip prevents the top surface of the semiconductor chip from directly contacting with the contact collect even at the time of vacuum suction by pressing the suction head of the contact collect against the top surface of the semiconductor chip.

Abstract: When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.

Abstract: A semiconductor integrated circuit device includes a memory array having first to Nth banks, where N is an integer greater than or equal to 2. The memory array further includes a redundancy block having first to Nth column recovery circuit blocks corresponding to the first to Nth banks, first to Nth row recovery circuit blocks corresponding to the first to Nth banks, first to Nth ECC fuse blocks corresponding to the first to Nth banks, and first to Nth ECC circuits corresponding to the first to Nth banks. During initial cycles, the first to Nth ECC circuits correct errors in column recovery fuse data in the first to Nth column recovery circuit blocks and errors in row recovery fuse data in the first to Nth row recovery circuit blocks by using ECC fuse data in the first to Nth ECC fuse blocks, respectively.

Abstract: The invention provides a signal processing semiconductor integrated circuit of the direct conversion system, which includes a dummy amplifier having the same circuit configuration as a low noise amplifier being the first stage amplifier, in which the DC offset calibrations on the subsequent stage amplifiers are carried out during shifting into the reception mode in a state that the low noise amplifier is deactivated and the dummy amplifier is activated. Thereby, the invention achieves to suppress generation of the DC offsets resulting from the leakage noises of the local oscillator during shifting into the reception mode, and to enhance the reception sensitivity.

Abstract: The invention provides a semiconductor integrated circuit device having a signal transmission path realizing high speed and low power consumption with a simple configuration. The device has a signal transmission path for transmitting a signal by discharging one of first signal lines corresponding to complementary input signals in a plurality of first signal lines precharged by a precharge circuit, and a self reset circuit for detecting the discharge level of the pair of signal lines corresponding to the complementary signals out of the plurality of first signal lines and operating the precharge circuit at a timing later than the period of discharging.

Abstract: The invention provides a bipolar transistor with improved performance. An insulation film comprising a silicon oxide film is formed by means of oxidation treatment on the side surface of an emitter aperture, and then an epitaxial layer comprised of SiGe is grown selectively in an aperture formed by removing a silicon nitride film so as to form under cut.

Abstract: Disclosed herein are an IC card and a microcomputer which have implemented the strengthening of security and the speeding up and enhancement of signal processing for the security. In an IC card, which is supplied with an operating voltage by an electrical connection between each of external terminals and a read/write device, and includes an input-output operation of data with an encoding process or a decoding process, a disturbance-aimed processing operation is included in the encoding process or decoding process to uniformalize timings provided to operate an internal circuit and its operating current. In a microcomputer having a module configuration including an input-output operation of data with an encoding process or a decoding process, a disturbance-aimed processing operation is included in the encoding process or decoding process to uniformalize timings provided to operate an internal circuit and its operating current.

Abstract: A semiconductor integrated circuit device having an internal voltage generating circuit which generates a voltage two or more times higher than an operating voltage while at the same time reducing the voltage applied to a device, thereby ensuring the device reliability. In a charge pump circuit driven by supply voltage VDD, a maximum of 2 VDD or a similar level voltage is applied between the drain and source of a MOSFET, the MOSFET being connected in series with a conduction MOSFET of the same type, the gate of which is supplied with VD?VDD, or a potential which is VDD lower than VD, the drain potential before its connection. The gate potential is obtained directly from a node in said charge pump which generates a voltage pulse synchronized with the voltage between the drain and source of that MOSFET, or through another rectifier device branched via a capacitor from the node.

Abstract: A magnetic disc storage apparatus including a magnetic head for reading information from a storage track on a magnetic storage disc driven to spin, a voice coil motor for moving the magnetic head above the disc, and a magnetic head drive system for executing a position control of the magnetic head by controlling driving current of the voice coil motor by a feedback control while monitoring a state of reading the magnetic head in which the magnetic head drive system includes multi-mode driving means for executing a linear drive mode for controlling, as an analog amount, the driving current of the voice coil motor when an amount of driving to move the magnetic head is small and executing a pulse drive mode for controlling, as a digital amount, the driving current of the voice coil motor when the amount of driving to move the magnetic head is large.

Abstract: A drive control system, with PLL control, drives a rotatable multi-phase sensor-less motor by switching a current of a field coil of each phase depending on the rotating phase of the motor. When the moto is driven, a desired phase is selected as a datection phase, and a voltage induced on the coil of the detection phase is detected when power is fed for a predetermined time to the field coils other than the detection phase. A magnetic pole position is detected from the amplitude condition of the detected induced voltage. Based on this detection, the power-feeding phase of the motor drive is determined. Power feeding and pole position detection are performed alternately.

Abstract: A semiconductor device comprising a plurality of wires for electrically connecting a plurality of electrode pads arranged on a main surface of a semiconductor chip along one side of the semiconductor chip to a plurality of connecting portions arranged on the main surface of a wiring substrate along one side of the semiconductor chip, respectively, wherein second wires out of the plural wires consisting of first and second wires adjacent to each other have a larger loop height than the first wires, one end portions of the second wires are connected to the electrode pads at positions farther from one side of the semiconductor chip than the one end portions of the first wires, and the other end portions of the second wires are connected to the connecting portions at positions farther from one side of the semiconductor chip than the other end portions of the first wires.

Abstract: A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen

Abstract: The semiconductor device includes a first current mirror circuit combining analog power sources and digital power sources to receive small amplitude signals and constant-voltage input signals, a second current mirror circuit for receiving a signal output from the first current mirror circuit and for level-converting the signal from analog power source to digital power source, a first node provided in the first current mirror circuit, a second node provided in the second current mirror circuit, and an inverter circuit for receiving a signal output on the basis of the voltage levels of the first node and the second node and for outputting a CMOS level signal.

Abstract: A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#1 through #13) are disposed on a card substrate (1) in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit (3) and an SIM (Subscriber Identity Module) card unit (4) are respectively exclusively connected and mounted to predetermined terminals of the connector terminals (#1 through #13). The memory card unit (3) and the SIM card unit (4) are respectively separately provided with areas for storing secrete codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level.

Abstract: In a device including regular circuits and redundant circuits, a plurality of relievable first wiring lines and a plurality of irrelievable second wiring lines are arranged in the same wiring layer as what constitutes the regular circuits and in the same direction, and at the same time the irrelievable wiring lines are arranged adjoining one another.

Abstract: A gate electrode of each MISFET is formed on a substrate in an active region whose periphery is defined by an element isolation trench, and crosses the active region so as to extend from one end thereof to the other end thereof. The gate electrode has a gate length in a boundary region defined between the active region and the element isolation trench which is greater than a gate length in a central portion of the active region. The gate electrode is configured in an H-type flat pattern. Further, the gate electrode covers the whole of one side extending along a gate-length direction, of the boundary region defined between the active region L and the element isolation trench, and parts of two sides thereof extending along a gate-width direction. The MISFETs are formed in electrically separated wells and are connected in series to constitute part of a reference voltage generating circuit.