Patents Assigned to Hitachi Tobu Semiconductor Ltd.
-
Patent number: 8278708Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: February 15, 2012Date of Patent: October 2, 2012Assignees: Renesas Electronics Corporation, Hitachi Tobu Semiconductor Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
-
Patent number: 7843001Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: August 11, 2009Date of Patent: November 30, 2010Assignees: Renesas Electronics Corporation, Hitachi Tobu Semiconductor Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
-
Patent number: 7361557Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: January 16, 2007Date of Patent: April 22, 2008Assignees: Renesas Technology Corp., Hitachi Tobu Semiconductor Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
-
Patent number: 7172941Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: November 10, 2004Date of Patent: February 6, 2007Assignees: Renesas Technology Corp., Hitachi Tobu Semiconductor Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
-
Patent number: 6858896Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: January 16, 2002Date of Patent: February 22, 2005Assignees: Renesas Technology Corp., Hitachi Tobu Semiconductor Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
-
Patent number: 6709890Abstract: In a method of manufacturing a high frequency module to be assembled by providing, on a wiring board, a chip part and a semiconductor pellet to be bare chip mounted and then mounting the chip part and the semiconductor pellet through soldering, the wiring board is separated from a heat block with the semiconductor pellet pressurized against the wiring board in a main heating portion heating and melting a reflow solder, thereby cooling a soldering portion. Consequently, the generation of a void in the soldering portion can be prevented and the connecting reliability of the soldering portion can be enhanced. In addition, a degree of mounting horizontality of the semiconductor pellet on the wiring board can be enhanced.Type: GrantFiled: February 15, 2001Date of Patent: March 23, 2004Assignees: Renesas Technology Corporation, Hitachi Tobu Semiconductor Ltd.Inventors: Tsutomu Ida, Akio Ishizu, Masakazu Hashizume, Isao Hagiwara, Yoshinori Shiokawa
-
Patent number: 6521993Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.Type: GrantFiled: April 18, 2002Date of Patent: February 18, 2003Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor Ltd., Akita Electronics Co., Ltd.Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
-
Patent number: 5220491Abstract: A module board has a supporting plate and slender lead pins having their first portions arranged substantially in parallel with one another on a plane substantially coplanar with the supporting plate. The supporting plate and the first portions of the slender lead pins are sandwiched between electrically insulating layer members. The supporting plate and the first portions of the lead pins are isolated from one another with an electrically insulating material between the pair of electrically insulating layer members. Second portions of the lead pins protrude from the pair of electrically insulating layer members. Through holes are provided one for each of the lead pins and through hole conductors are formed on the inner walls of the through holes.Type: GrantFiled: April 8, 1991Date of Patent: June 15, 1993Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor Ltd.Inventors: Toshio Sugano, Seiichiro Tsukui