Abstract: A method for manufacturing a metal-oxide-semico nductor field effect transistor (MOSFET) having a drain and a source each of which has a lightly doped area, an enhanced lightly doped area and a heavily doped area is disclosed.

Abstract: A new structure of a non-volatile semiconductor memory cell array and a method of fabricating the memory arrays. The circuit layout of the memory array not only comprises of the conventional floating gates, control gates, cell sources and cell drains, but also adds the local source regions to increase the coupling ratio. Besides, the new design can reduce the number of metal contact windows, further increase the packing density of the memory array. Furthermore, an additional isolation region is formed between two bit lines so as to increase the distance between two bit lines, which can minimize the possibility of cross talk due to shirking spacing.

Abstract: The present invention provides a method for accessing a memory device and a memory accessing device. The method includes a) providing the memory device having a plurality of memory sub-spaces respectively having a plurality of address ranges; b) respectively assigning a plurality of base addresses to the plurality of memory sub-spaces; c) inputting an access address; d) respectively operating the base addresses with the access address to obtain a plurality of operated results; and e) accessing one of the memory sub-spaces if a specific one of the operated results falls within one of the address ranges corresponding to the one memory sub-space.

Abstract: An intelligent bias voltage generating circuit capable of providing an electronic device with a reliable bias signal includes a power input terminal which is electrically connected to a power generating device for providing a power input, and a bias voltage generating circuit which is electrically connected to the power input terminal for responding to power fluctuations and generating a bias voltage signal output by a multi-section linear variation method.

Abstract: An adjustable-period dual-tone multifrequency (DTMF) generator, which includes a plurality of programmable counters or up/down counters, a control unit, a memory unit for storing data, a digital adder, and a digital-to-analog converter. The programmable counter and the control unit are combined together to form into at least two programmable counting address generators, in which the circuit is a digit-process circuit for overcoming the problem of signal distortion that usually exists in an analog circuit.

Abstract: A method is provided for manufacturing a polysilicon with a relatively small line width. The method includes steps of: a) forming a first layer of photoresist with a line pattern having a first line interval and a first line width over the polysilicon; b) etching a portion of the polysilicon for forming the polysilicon with a second line interval x and a second line width y respectively equal to the first line interval and the first line width; c) forming a second layer of photoresist with a third line interval and a third line width over the polysilicon; d) etching another portion of the polysilicon for forming the polysilicon with a fourth line interval x`, equal to the third line interval, and a fourth line width y`; e) depositing a polysilicon film over the polysilicon with the relatively small line width; and f) etching a portion of the polysilicon film to form sidewalls of the polysilicon with the relatively small line width for adjusting the relatively small line width of the polysilicon.

Abstract: The present invention relates to methods and devices for generating cycled waveforms of nonsingle period, and more particularly to an improvement from the one-way counter used by conventional cycled waveform generator of nonsingle period into an up-down counter or a programmable up-down counter, along with an adder/subtracter. Thus, only the varied values in waveform relative to a DC level have to be filled into a table, and then the varied values in waveform (i.e. the digital waveform sampling values) are input into said adder/subtracter to obtain a periodic digital values by adding/subtracting with a predetermined DC level. Finally, cycled waveforms of nonsingle period are obtained by digital-to-analog converting of said digital values. With the methods and devices of the present invention, not only the fillings in said table can be decreased to reduce the cost, but also the DC output level can be fixed or adjusted arbitrarily for convenient signal processing.

Abstract: Disclosed is a digital filter having phase-adjustment ability, and more particularly to a digital filter system which can restore the phase of data transmitted via digital radio communication and thereby enhances the noise-immunity of data and the correct bit decision. The digital filter mainly includes a hold back data unit, a digital filter unit, and a signal phase modify unit to remove noises in the signals and to modify and restore correct digital wave-form signals. The digital filter having phase-adjustment ability is suitable for use in digital radio phones, pagers, etc. commonly found in the radio communication systems.

Abstract: A method for improving the electrical property of gate in polycide structure is disclosed. First, a gate oxide layer is formed on the surface of the silicon substrate. The following procedure acts as one of the key points for the invention comprising the process steps of (1) forming a highly-doped polysilicon layer on the gate oxide, (2) forming an undoped amorphous silicon layer on the polysilicon layer, and followed by (3) forming a tungsten silicon layer on the amorphous silicon. Next, annealing at high temperature and in short time is performed. Such a stacked gate structure has low resistance and can solve the following problems: (1)peeling of tungsten silicide after annealing, (2) degradation of the electrical property of gate due to the diffusing and penetration of fluorine atoms coming from tungsten silicide.

Abstract: A sensing circuit for detecting data stored in a memory cell of an EEPROM by current detecting method is disclosed. The sensing circuit includes a constant current source supplying circuit for supplying a constant current. A loading circuit generates a current the same as the constant current generated by the current source supplying circuit when the memory cell sends out a logic low state signal, so that the data accessing speed during reading the data stored in the memory cell is increased.

Abstract: A cycle-modulating DTMF generator for generating a DTMF signal; the generator comprises a programmable time-pulse generator, counters or up/down counters, a memory unit for storing data, a digital adder, and a digital-to-analog converter. The circuit of such generator is substantially a digital circuit so as to overcome the problem of signal distortion, which usually exists in an analog circuit.

Abstract: A voltage detector circuit for instantaneously detecting abnormal voltages in a micro controller includes a voltage detection circuit connected between the power supply and reset voltage ends of an internal circuit of the micro controller so as to instantaneously detect changes in the power supply, without the time delay associated with the external low pass filter that supplies the reset voltage. The detecting circuit is a logic "NOT" gate which has a power supply connecting end connected to a reset voltage end of the internal circuit, an input end connected to the power supply end of the internal circuit, and an output end connected to a cooperating input end of the latch circuit, so that the latch circuit latches a signal output by the voltage detector whenever an abnormal power supply voltage is detected, and outputs a flag signal to the micro controller to effect an instantaneous reset of the micro controller.

Abstract: The present invention provides an encoding-decoding method for an actuating system having an encoding device, a decoding device, at least one code having a counter code, and an actuating device. The method includes steps of: a) executing a first logic operation on said at least one code for obtaining a specific expansion code in said encoding device to form a transmission code including said specific expansion code and said counter code; b) transmitting said transmission code to said decoding device; and c) executing a second logic operation on said at least one code and said counter code to obtain an operated code for identifying whether said operated code is matchable with said specific expansion code in said decoding device.

Abstract: A method of fabricating a universal zero layer photomask of an integrated circuit is disclosed. With this method, only one universal zero layer mask is required for all the integrated circuit products; thus, the production cost can be reduced. In this method, the alignment marks and one or more vernier patterns are located near the edge of the effective exposure field of the wafer which takes up only a very small area of the wafer. Furthermore, the zero layer layout of the product also places the alignment marks and the vernier patterns in the same corner as the photomask. During the alignment, the wafer moves back and forth in both X and Y directions so as to match the previously recorded alignment marks positions on the mask.

Abstract: A multi-function telephone dialer display device which is equipped with a display screen for displaying the use status and the caller identification information, and a dialer for responding to data input and for generating a data signal to the display screen to display the corresponding use status. When dialing with numerical keys, with standard non-numerical keys or when setting up a function, the data signal is coded into a numerical code representing the original digit, coded into a standard non-numerical code representing the original non-numerical keys or coded into a function key code representing the function, respectively.

Abstract: An interface control device to be mounted between a TV game equipment and a PC interface card. The interface control device includes three main signal generating circuits and an address decoding circuit to process various signals and send a data-transmission acknowledgment signal to an expansion slot of the TV game equipment such that signals generated from the expansion slot interface of a TV game equipment can be converted into signals recognizable by the PC standard bus interface so as to allow the TV game equipment to directly access data via an interface card originally inserted on a PC standard bus, and enhance the utilizability of the expansion slot interface of the current TV game equipment.

Abstract: The present invention is related to an interface circuit for transmitting data corresponding to a specific address from/to a decoding memory unit, includes a bit-selection circuit pre-set therein a transmission mode, and a processing circuit electrically connected to the bit-selection circuit for transmitting the data according to the transmission mode. The present invention also relates to methods for reading out and writing in data corresponding to a specific address from/to a decoding memory unit.

Abstract: A method of fabricating high step alignment marks on a twin-well integrated circuit. An alignment mark photoresist pattern is formed overlaying the nitride layer using lithography technique. The nitride layer is partially etched to form a nitride alignment pattern using the alignment mark photoresist pattern as a mask. After the formation of N-well and P-well regions using lithography technique, the N-doped and P-doped impurities are subject to a thermally drive in process to activate and form N-well and P-well regions, respectively. At the same time, the pad oxide layer overlaying the N-well and P-well regions and the region not covered by the nitride alignment pattern is converted to a thermal oxide layer. The thermal oxide layer can be removed to reveal a recessed portion on the surface of the P-type silicon substrate, whereby the thickness of the nitride layer plus the depth of the recessed portion causes high step alignment marks to be formed.

Abstract: A monitor-controlling device is disclosed. The monitor-controlling device, used for a system having a monitor and a first circuit, includes a buffer for storing data from the system; a decoder electrically connected to the buffer for receiving and decoding the data; a bi-directional transmitter electrically connected to the buffer for providing the buffer with a path to transmit the data to the first circuit; and a controlling circuit electrically connected to the bi-directional transmitter for controlling the path on or off.

Abstract: The present invention is related to a system reset device setting the reset status of a system in response to a reset signal. The system reset device according to the present invention includes a power-stability detecting circuit for detecting the stability of a power signal generated by a power source and provided for the system, an oscillation-stability detecting circuit for detecting the stability of an oscillation signal generated by an oscillator and provided for the system, and a level-control circuit electrically connected to the power-stability detecting circuit and the oscillation-stability detecting circuit for controlling a level state of the rest signal in response to the stability of the power signal and the oscillation signal. The level-control circuit includes an OR gate, an AND gate, and an S-R latch for performing the level state control of the reset signal.