Abstract: A device for raising voltage comprises a first element for providing a first output pin with a voltage raise in response to a first voltage change at a first input pin, and for providing a second output pin with a voltage raise in response to a second voltage change at a second input pin; and a second element for driving, when the voltage at the first output pin becomes higher than the voltage at the second output pin due to the first voltage change at the first input pin, the second output pin to maintain a voltage keeping pace with the voltage at the first output pin, and for driving, when the voltage at the second output pin becomes higher than the voltage at the first output pin due to the second voltage change at the second input pin, the first output pin to maintain a voltage keeping pace with the voltage at the second output pin.

Abstract: An apparatus for page mode programming of an EEPROM cell array applications is described. The apparatus comprises a control gate potential control means and a bit line potential control means. The control gate potential control means is connected to the control gate of the EEPROM cell to select the potential for the control gate of the EEPROM cell, while the bit line potential control means is connected to the bit line of the EEPROM cell to select the potential for the bit line. A bit line of the EEPROM cell is first selected by a bit line control signal, then a control gate control signal determines whether provides the high voltage to the control gate of the EEPROM cell.

Abstract: The present invention is related to an enhanced high density Read-Only-Memory (ROM) device with select gate. A thin oxide layer is deposited on the ROM cell matrix and it is extended to the select lines which is on the top and bottom side of the ROM cell matrix to form the select gate. The ROM cell matrix can be organized more flexible by using the buried layers to pick out the unwanted gates. The metal contact can be directly made in this extended region too. Thereafter it reduces the manufacturing cost and achieves a high speed and density and simple process device.

Abstract: A method of fabricating alignment marks on an integrated circuit device including steps of: forming first pad oxide layer and first nitride layer on a P-type semiconductor substrate; coating and patterning first photoresist layer by lithography; partially etching first nitride layer to form first nitride pattern by first photoresist etching mask; and ion implanting N-type ions to form an N-doped region; coating and patterning second photoresist layer by lithography; partially etching first nitride pattern to form second nitride pattern; and ion implanting P-type ions to formed a P-doped region. Next, performing thermally drive in N-type and P-type impurities to form N-well and P-well regions, and growing an oxide layer simultaneously. Finally, the height difference between the oxide layer and the second nitride pattern producing a ladder topography can be used as an alignment mark for the succeeding lithographic processes.

Abstract: A remove control device that has voice recognition and user ID restriction functions equipped with a receiver is provided. The device includes a radio frequency (RF) receiving circuit, a demodulator, a voice input control device, an analog to digital conversion signal control unit, a buffer, a memory, a voice recognition processing unit, an instruction verification device, and an output control device. When the receiver is in a voice training mode, the signal characteristics of the voice command from the user can be stored in a memory. When the receiver is in an instruction execution mode, the receiver receives signals transmitted from the emitter, recognizes and compares the signal with the original signal stored in the memory during the voice training mode and determine if it is from an authorized user. Only after the identification matches the instruction verification device that verifies the received instruction, the output control device outputs a corresponding control signal.

Abstract: A timer which provides both the surveying and counting functions. It contains a counter, a multiplexer, an edge-triggered controller, a time-base latching circuit, and a pulse-detecting circuit. It not only can be used as a timer, but can also be used as a counter to count the number of the external signals so as to detect the width of an external signal.

Abstract: A computer keyboard power saving method includes sensing if there is keystroke action taking place. When time period of no keystroke action exceeds a pre-set threshold, power supply to the keyboard will be shut down automatically. When a keystroke action is detected, power supply to the keyboard will be resumed instantly. Thus can save energy when keyboard is idle from time to time.

Abstract: A high speed division method and apparatus that does not require the use of dividers are provided. The method and apparatus utilize a binary shift-add technique to simplify a divisional computation process and to enable computational error to be contained in a predetermined range, and to obtain a higher computing speed. The apparatus includes a divisor left-shift apparatus for inputting a divisor and to left-shift the divisor, a dividend left-shift apparatus for inputting a dividend and to left-shift the dividend, a left-shift controller for controlling the left-shift motion of the divisor, a quotient right-shift apparatus for inputting the indexes from a division table and then right-shift the quotient. The apparatus utilizes left-shift or right-shift to achieve a multiplication or division by 2.

Abstract: A memory table look-up method for executing a table look-up instruction in an active program uses an instruction buffer executing device, a controller and a data register to output table look-up data from a memory to the data register. The method includes causing an instruction buffer executing device to execute a table look-up instruction obtained from the memory and pre-stored in the instruction buffer executing device in a first cycle to generate and output a table look-up signal, and to cause the controller to output a next instruction being an instruction next to the table look-up instruction in the active program from the memory to the instruction buffer executing device in response to the table look-up signal.

Abstract: The present invention relates to a reset signal generator adapted to be used with a microprocessor for generating a reset signal to initialize the microprocessor, which includes an oscillator to generate a fixed clock signal, a counter electrically connected to the oscillator for generating a cyclic signal in response to the fixed clock signal and outputting the reset signal at an end of a period of the cyclic signal, and a clear signal generating device electrically connected to the counter and outputting a clear signal for the counter in response to an output signal from the microprocessor. The present invention ensures that when the microprocessor is abnormal or down it will be initialized by the reset signal.

Abstract: A voice-dialing device without additional power supply can generate articulate voice signal upon dialing; such device can provide a function of voice dialing, and a function of confirming the dialing. In dialing operation, the device can provide a correct dialing by using the voice dialing as an auxiliary means; after dialing, a user can confirm the number dialed so as to ensure a user to control the dialing operation and the correctness of a number dialed.

Abstract: This present invention relates to a level-shift type digital to analog converter including a selection circuit, a multiple voltage level generation circuit, a stabilization circuit and a level-shift type buffer stage circuit. The multiple voltage level generation circuit is composed by a divided-step voltage output circuit and a level voltage output circuit, for generating a plurality of voltage levels to directly output to a level-shift type buffer stage circuit or alternatively, to be processed through voltage selection in order to respectively output the divided-step voltage output values and the level voltage output values to a level-shift type buffer stage circuit. A stabilization circuit generates a reference voltage or a reference current insensitive to the power supply voltage V.sub.DD for other elements of the converter.

Abstract: A data shift control circuit for a shift register in response to a logic operation command code is disclosed. The shift register includes a first register and a second register and the logic operation command code includes a first portion and a second portion. The circuit includes a first decoder for decoding the first portion to transmit a move signal; a second decoder for decoding the second portion to transmit a control signal; a control signal channel, electrically connected to the first register and the second register, for allowing the first register and the second register to receive the control signal and for allowing the shift register to execute a first action; and a move signal channel, electrically connected to all registers of the shift register for allowing the all registers to receive the move signal and for allowing the move register to execute a second action.

Abstract: The present invention is related to a flexible IC layout method utilized for an IC having a plurality of logic gates in a first direction connected with a plurality of logic gates in a second direction wherein each of the logic gates has at least one polysilicon region and each of the logic gates in the first direction has an output serving as an input of a corresponding one of the logic gates in the second direction, which includes a step of forming input terminals for the logic gates by ion implantation. The present invention is flexible because the addition or deduction of the number of the input terminals according to the present invention can be achieved by ion implantation.

Abstract: A method of compressing an integer multiplication table including the steps of first eliminating one of the two symmetrical and identical sections in the table, eliminating the products of 0 multiplier and 0 multiplicand, moving the product of the multiplier having an index of n into the location of index (n-1) for the multiplier, using one-half of the number of the largest multiplier as the largest multiplier index for the compressed multiplication table, moving into the non-continuous memory space of the compressed multiplication table by a page-filling method the product of the largest multiplier index value that is larger than the compressed multiplication table such that the multiplication table after compression can be stored on the same page.

Abstract: A cost effective waveform-generating apparatus that generates accurate and precise waveforms is disclosed. The present waveform-generating apparatus includes a memory for storing a sequence of sampled amplitudes of a waveform, said sampled amplitudes constituting at least two periods of said waveform; a counting circuit, electrically connected to the memory, responsive to a clock signal for generating counting signals; a controlling circuit, electrically connected to the memory and the counting circuit, responsive to the counting signals for controlling the memory to output the sampled amplitudes recurrently; and a digital to analog converter, electrically connected to the memory, for converting the recurrent sampled amplitudes into an analog output.

Abstract: A binary multiplication method utilizing a combined table lookup and long multiplication to simplify the multiplication procedure, to improve the computational speed, and to save half of the memory space normally required. The method is executed by first moving the least significant bit (LSB) of the multiplier to another memory device before the start of the computation and then using the shortened multiplier in the multiplication operation since the multiplier is reduced by one bit, the memory space required for the multiplication table is reduced by half. The method does not require the use of a multiplying device and only needs small memory space. The manufacturing cost of a microprocessor can be reduced accordingly.

Abstract: A method and apparatus for determining the degree of membership in a fuzzy inference by using a subtractor and a divider without the need for a complicated multiplication, division circuit or software that is normally required in a conventional method. A fuzzy inference database for the degree of membership is first established in a microprocessor by a fuzzy inference method, the membership function in the fuzzy database has a range between 0 to 1 at full scale for the degree of membership function. When the microprocessor detects an input data, a slope distance ratio and the corresponding coordinates are determined and compared using the input data and the fuzzy database established in the microprocessor. The ratio determined by the greatly simplified method is the degree of membership function.

Abstract: A method of fabricating a twin-well integrated circuit device to implant the dopants directly through the nitride layer including steps of: The pad oxide layer and nitride layer are formed on a P-type semiconductor silicon wafer. Then, the alignment mark photoresist pattern is formed by the conventional lithography technique, where the alignment mark region is in clear field, while other regions are in dark field. Next, the nitride layer is patterned by plasma-etching technique to form the nitride alignment mark. The N-well region is formed by lithography and ion-implantation techniques. Thereafter, the P-well region is formed by lithography and ion-implantation methods again. Next, the active device region photoresist is formed by lithography technique. The nitride layer is partially etched to open the windows by plasma-etching technique. The P-well region photoresist is then formed, followed by the deep-implantation process.

Abstract: The present invention provides a fixed resistance sense-routed high density parallel ROM device for maintaining the resistance of a buried N+ region on a sense route constant. When data is read from a ROM cell matrix, the selection of different ROM cell transistors does not change the resistance of the buried N+ region on the sense route and thus enables a simplified design of a sense amplifier. The inactive select gate or transfer gate that is activated by the select line can be isolated by ion implantation for forming a buried P+ isolation and thus avoiding the narrowing or the cutting-off of the width of the active transfer gate or select gate due to ion diffusion.