Abstract: A method for speeding up JPEG quantization operations in image compression for discrete cosine transform encoding operations in JPEG image compression. The quantization calculations are performed to obtain descriptors for Huffman encoding. The quantization calculations utilize a modified quantization table which is derived from an original quantization table by inversing each element of the original quantization table and then mutiplying 2.sup.n and then rounding off. The matrix composed by discrete cosine transform coefficients multiplies the modified quantization table to derive a new matrix. Then, each element of the new matrix is right shifted n bits to derive quantized discrete cosine transform coefficients. Then, Huffman encoding is performed to accomplish discrete cosine transform encoding.
Abstract: A new structure of a triple-well non-volatile semiconductor memory cell array and a method of fabricating the memory arrays are described. The circuit layout of the memory array not only includes the conventional floating gates, control gates, cell sources and cell drains, but also adds the local source regions to increase the coupling ratio. Besides, the new design can reduce the number of contact windows, further increasing the packing density of the memory array. The key point of the method is the triple-well formation inside the silicon substrate that lowers the operational voltage of periphery circuit. Furthermore, there are two additional isolation regions between two adjacent metal lines, which can minimize the possibility of cross talk due to shirking spacing.
Abstract: A test method for charge redistribution type digital-to-analog and analog-to-digital converters by utilizing the special characteristics of a DAC or ADC such that the accuracy and linearity of the converted signal is only determined by the internal capacitance ratios of the converter, and that the accuracy and linearity are not related to the test reference voltage, the test voltage and the noise signal of the test machine. The test method utilizes a principle of capacitance comparison to directly compare the capacitance ratios in a converter in order to determine the accuracy and linearity of the converted signal. The present invention method enables an effective reduction in the test time and test steps required and an increase in the test efficiency.
Abstract: A module and apparatus for measuring temperature related properties of an SRAM IC includes circuitry for controlling writing of data to and reading of data from a pair of SRAM ICs, one of which is a control and the other of which is the SRAM IC being tested. The circuitry includes an address counter, a logic controller, two input buffers, two output data latches, and a data comparator, the effect of temperature on data input through the input buffers under control of the logic controller and address counter being analyzed by comparing data output through the data latches. In addition, the apparatus includes two separate seats for the respective SRAM ICs, one of which is subjected to a constantly controlled temperature and the other of which is subjected to a varying ambient temperature.
Abstract: A method for increasing the thickness of field oxide layer is provided. At first, a layer of pad oxide and a layer of silicon nitride mask are defined on a semiconductor substrate, and then a field oxide layer, which isolates active device regions, is formed. After the layer of pad oxide and the layer of silicon nitride are removed, a layer of silicon oxide is formed overlying the field oxide layer. The mentioned silicon oxide layer can increase the thickness of field oxide layer for effectively isolating active device regions without enlarging Bird's Beak. The present invention can also effectively improve the Gate Coupling Ratio in a Flash EEPROM.
Abstract: A memory circuit with auto redundancy, offers the user to repair the defective memory by auto redundancy. The present invention implicates a counter to count the times of the programming verify loop. The user can set the times of the programming verify loop less then the prior art's. When the setting times of the programming verify loop are achieved, the memory cells enable the redundancy cells automatically. Moreover, this invention can use the EPROM, EEPROM and Flash Cells to be the fuse directly to store the address data. So this invention will be more convenience for user to repair the defective memory, and reduce the recording process efficiently.
Abstract: A gain estimation method for an LPC vocoder which utilizes shape indexes. The gain is estimated based on the envelope of the speech waveform. The gain is estimated such that the maximum amplitude of the synthetic speech just reaches the speech waveform envelope. The gain during voiced subframes is estimated as the minimum of the absolute value of ratio of the envelope and the impulse response of the LPC filter. The gain during unvoiced subframes is estimated as the minimum of the absolute value of the ratio of the envelope and the noise response of the LPC filter. The method results in a fast technique for estimating the gain.
Abstract: A differential amplifier with double output stages used to eliminate the charge injection noise and switching capacitor noise is disclosed. This system includes an input stage, a middle stage, a first balanced output stage, a second balanced output stage, a negative feedback network and a common mode feedback network. The input stage processing the differential input signal, connects to the middle stage and the negative feedback network which increasing the gain of input signal and connects to the first balanced output stage and second balanced output stage. The first balanced output stage is connected to the negative feedback network for stabilizing the frequency response, and the second balanced output stage is connected to the common mode feedback network for controlling the common level of double terminals output into a setting range of voltage. Thus the output signal of the amplifier will be a clear waveform without redundant noise for next connecting circuit.