Abstract: A switching mode power supply where an input rectified voltage feeds in chopped mode the primary winding of a power transformer under the control of a transistor turned on by voltage pulses periodically generated by an oscillator directly fed by the input voltage and applied to the transistor through a control transformer, said transistor being turned off by a voltage pulse generated by regulating circuits fed by the output voltage of the power supply and applied to the transistor through the same control transformer which is further provided with a winding where anelectromotive force is induced which is proportional to the current flowing through the primary winding of the power transformer.

Abstract: A digital data separator for use with apparatus for recovering binary information recorded on a movable media in frequency modulation (FM) or modified frequency modulation (MFM) comprises a measurement unit which for each read pulse received as an input provides a code representing the actual duration of an interval N between read pulse n and the preceding read pulse n-1 and a speed error correction unit which corrects an actual interval duration relative to the speed error of the movable media. The separator further includes a peak-shift recovery unit which provides as an output, nominal duration information related to interval N based on the corrected interval duration and on the peak-shift of pulse n-1, determined by taking into account the corrected duration of an interval N-1, a preceding interval N, and the nominal duration of intervals N-1 and N-2 preceding interval N.

Abstract: A digital data separator for use with apparatus for recovering binary information recorded in FM or MFM on magnetic media comprises a measuring unit which in correspondence with a read pulse n, supplies information representative of the actual duration of interval N between pulse n and the previous read pulse n-1.

Abstract: A digital apparatus for data recovery system wherein data is recorded in FM or MFM code on magnetic media, comprises a measuring unit that in correspondence of a read pulse n as an input, supplies as an output, information related to the actual duration of interval N between pulse n and the previous read pulse n-1. A recovery unit for the magnetic media speed error relative to a nominal speed corrects the duration according to a code representative of the magnetic media speed error and a peak shift recovery unit which, according to the peak shift of pulse n-1, determined on the basis of the time history of the most recent pulses n-2, n-3, n-1 and the corrected duration, supplies as an output, nominal duration information related to this corrected duration and information representative of the direction and the amount of the peak shift of said read out pulse N-7.

Abstract: A microprocessor system is disclosed wherein a microprocessor has a multiplexed address/data bus which communicates with a plurality of memory and input/output devices. A demultiplexing register permits the demultiplexing of the microprocessor address/data bus, while a decoder permits the selection of one of the system devices during a microprocessor external operation in response to the most significant address bits. The system output devices comprise a plurality of TTL outputs whose inputs are connected to the output of a demultiplexing register where, during a microprocessor external operation, information representative of the less significant address portion is latched. Datum information transfer to an output TTL gate is obtained by having an external operation executed by the microprocessor so that the most significant address bits select the gate and the less significant address portion represents the datum to be transferred.

Abstract: A digital apparatus recovers data recorded in FM or MFM on a magnetic media moving at a normal speed in which the reading of the media provides a sequence of timing/data pulses at variable intervals, which differ from a nominal interval due to speed error and magnetic "peak-shift". The apparatus provides identification of a nominal interval between read out pulses and the reconstruction of a correct stream of pulses properly located within a window signal. It includes a digital measurement unit which at each read out pulse n received in input supplies at an output a code indicative of the actual duration of the interval N between the pulse n and a previous pulse n-1; and a speed correction unit which corrects the measured duration of the interval N relative to speed error detected by the digital measurement unit during reading of a synchronization bit field.

Abstract: A microprogrammed control apparatus for dot matrix serial printers and related printing method which allows increased horizontal resolution of the printing matrix and therefore the printing quality consistent with the restriction that no printing element can be actuated before a previous energization of any printing element has been completed. The increase of the horizontal resolution is obtained by using a character description matrix with high resolution and logic circuits responsive to binary configurations read out from such matrix. In a preferred alternative, the increase of the horizontal resolution is obtained by using a "compressed" character description matrix containing a plurality of printing patterns, one for each of the columns where printing has to be performed (hereinafter "column to be printed") and a corresponding plurality of codes, each related to a printing pattern and representative of the distance/time interval between the column to be printed and the previous column to be printed.

Abstract: Data processing system architecture in which a central processing unit (CPU) and a plurality of input/output processors (I/OP), said I/OPs being connected in parallel through a bus can have access to a common working memory, under control of a memory access control unit, through a set of tridirectional gates directly connecting memory to the CPU or to the bus without interposition of registers, drivers, receivers, except said tridirectional gates, between the internal CPU channel and the memory channel. The control unit periodically monitors, in synchronism with internal CPU cycles if memory access requests from the I/OP are pending and, absent such requests, the CPU may activate memory cycles in synchronism with its internal cycles without preamble diagloue and access waiting time.

Abstract: A needle end ruby of a needle printing head where the printing needle writing ends are arranged along one or more parallel columns is comprised of two or more plates juxtaposed on one or more planes. Each plate is rigidly fixed to the contiguous plate or plates. The ruby guiding openings for one column of the needle writing ends are obtained by shaping and grinding the sides along which two plates are juxtaposed and fixed.At least one of the plates comprising the ruby has a different height in relation to the remaining juxtaposed plate(s). Thus the ruby presents two ground surfaces used for accurately positioning the ruby into a housing in the nose end of a guiding needle head.Alternately the guiding ruby, though comprised of plates of equal height, can still present two reference ground surfaces by juxtaposing and fixing at least two of the plates in a staggered manner so as to expose precisely ground surfaces utilized to accurately position the ruby into its housing.

Abstract: Computer control memory apparatus is disclosed wherein the microinstructions may selectively have a variable bit length. A main control memory stores microinstructions having a basic length and they are read out and stored in a microinstruction register. Microinstruction prefixes are obtained from more than one source and are selectively added to the basic length microinstruction in the microinstruction register to create longer microinstructions, as needed, for controlling the operation of the computer. The microinstruction prefixes may be obtained from a secondary control memory that is addressed at the same time as the main control memory, or may be obtained from a field of N bits which is a part of a previous microinstruction read out of the main control memory and saved in an expansion register, or may be all zeroes when it is not desired to expand a microinstruction of basic length read out of the main control memory.

Abstract: A multicolor inked ribbon cartridge for an impact serial printer comprising a ribbon housing body and two arms protruding from such body to allow the interposition of a ribbon portion between a printing head and a printing support for the whole length of the platen when the cartridge is rotatably attached to the frame of an impact serial printer by means of two lateral cylindrically-shaped projections provided on the body of a cartridge thus permitting rotation of the body around a common axis of said cylindrical projections, parallel to the platen. The cartridge rotation around such axis and therefore the positioning of a suitable multicolor band between the printing head and printing support is assured by a cam actuated by a motor and interacting with the body of such cartridge. The cartridge is further provided with a string made tight between the ends of its arms upon the multicolor ribbon portion which is interposed between the head and printing support.

Abstract: An armature group for mosaic printing head has a plurality of armatures wherein each armature which is part of an actuation electromagnet associated with one of a plurality of printing needles, is fixed to an elastic arm of a spring steel spider having as many arms as there are armatures. The spider, besides performing an armature positioning function allows the armature group to be handled as a unitary element which is easy to assemble. The thrust arm of each armature further has a double bend so that the plane between such arm and the corresponding needle head is perpendicular to the axis of the needle and passes through the fulcrum of the armature. This minimizes the buckling force which the needle has to undergo during the actuation phase. The construction of the armature group can be accomplished by a completely automated manufacturing process.

Abstract: An improved single error correction circuit for a system memory storing in each of its addressable locations a data word and a corresponding error correcting code, which when read out from memory are fed to a syndrome generator which generates in output an error syndrome indication, comprising a set of registers arranged in banks, a first register in each bank for storing a prefixed portion of the data word read out from memory, the other registers in each bank for storing all the possible data configuration obtained from the prefixed portion of the data word stored in the first register of the same bank by inverting one data bit, so that a corrected read out data word is available in such registers in advance of syndrome indication which decoded, provides selection signal enabling one selected register per each bank to output, with minimum delay the latched portion of the data word.

Abstract: A multiple output switching power supply wherein the voltage at a main output which couples to a main secondary winding of a transformer is regulated by pulse width modulation of the current flowing in the primary winding of the transformer and wherein the voltage at an auxiliary output which couples to an auxiliary secondary winding of the transformer is regulated by pulse width modulation of the current flowing in the auxiliary winding. The pulse width modulation is performed in synchronism with a preestablished turn-on delay of the control switches which control current pulses in the primary winding as to the turn-on of the switches which control current pulses in the auxiliary winding. Besides avoiding the need for a filter between the auxiliary winding and the related control switch, this form of synchronization reduces switching power losses, current spikes and induced radio frequency emission.

Abstract: Computer modular housing with retractable stabilizers comprised of bearing feet shiftable relative to each other in a parallel direction, each of said bearing feet is independently movable laterally relative to the others so as to increase the frame bearing area and therefore increases the frame stability. They may also be retracted to a position which permits the assembly of modules against walls or other frames in order to form systems of juxtaposed modular units.

Abstract: This invention pertains to a power FET control circuit which operates at higher switching frequencies for reducing the output voltage ripple. The control circuit provides two pulse control signals each shifted 180.degree. out of phase, each of such signals having a fixed frequency and a duty-cycle ratio which varies up to a maximum of 50%.

Abstract: An asynchronous bus multiprocessor system where a plurality of microprogrammed processors communicate with a working memory through a common bus. Microinstructions are read out from working memory. At least one of the processors, in addition to conventional bus interface registers for latching of data, address and commands to be forwarded to the working memory through the bus, is provided with an additional interface register, devoted to the latching of a microinstruction address for a microinstruction to be read out from the working memory. The system is further provided with a multiplexer for selectively loading a microinstruction register either from a microprogram control memory or from the system common bus, via a direct path established between the system common bus and an input set of the multiplexer.

Abstract: Interrupt control apparatus in a data processing system for acknowledging on a priority basis one among several possible asynchronous interruptions (INT1, INTN), such apparatus comprising a priority network (5), a latching (7) and a validation circuit (11,12). The priority network directly receives on its input terminals the asynchronous interrupt signals and provides on its output terminals a binary code corresponding to the highest priority interrupt present on its input terminals. The interrupt code is latched in the register and is present on its output terminals. The code latched in the register is used by a validation circuit as a selection code of the related input interrupt signal. If such a signal is present, the code is validated, i.e., it is transferred to the central unit of the system. If the selected interrupt signal is not present, the code is not validated.

Abstract: A probe support for a test fixture of printed circuit artworks comprising a base plate defining a supporting plane for connecting pins of a plurality of probes, a corresponding plurality of connecting elements, a cover plate designed to protect the contact tips of the probes and of connecting elements when the probe support is not to be used, etc. The base plate and the cover plate may be alternatively removed for set up and use respectively; the probes and the connecting elements being restrained to and protected by either the cover plate or the base plate. In this way both assembly of the probe support and the wiring harness between the probe pins and the pins of the connecting elements is made easier. The probe support further comprises a plate provided with a plurality of holes which house and axially guide the contact tips of the probes during active test.

Abstract: Electromagnetic printing group for a dot matrix printer where the armature movement towards the rest position isdamped by a counterarmature interposed between the armature and a resilient element defining the rest position so that the air cushion interposed between counterarmature and armature provides a first damping action followed by the damping caused by the ballistic impact between armature and counterarmature and finally by the resilient damping of the residual energy of the armature and counterarmature.