Abstract: A memory system wherein data is stored along with a SEC-DED error detecting and correcting code. Means are provided for selecting either a direct readout path for data from the memory when no readout errors have been detected for the memory address being accessed, or an alternate readout path including circuits for checking and correcting errors when an error condition has been detected. An auxiliary memory is provided for storing error flag bits indicating memory zones which have produced erroneous readouts, whereby the system is controlled such that high speed direct read cycles are executed for no-error memory zones and optimum memory accessing time is achieved without sacrificing the reliability achieved through use of the error correcting codes.

Abstract: A symptom compression device receives binary coded information including bits signifying symptoms present in the course of each operating cycle at selected points in an integrated logical network, microprocessor or the like. The device includes a first register, a second shift register, an EXCLUSIVE OR logic network, and a display. The binary coded information is received on parallel inputs of the first register and applied from parallel outputs of the first register to a set of inputs of the EXCLUSIVE OR network, a second set of inputs which is connected to at least some parallel outputs from the second shift register. A set of outputs from the EXCLUSIVE OR network is connected to parallel inputs of the second shift register. In each cycle, the bits in the second shift register, which accumulate information representative of symptoms, are shifted in one direction and are recirculated. The display is connected to the parallel outputs from the second shift register.

Abstract: A paper feed mechanism for multiple copy, impact-type printers used in data processing systems, wherein both the platen and the paper advancement tractors are positively driven to avoid tearing of the paper and clogging of the feed mechanism.

Abstract: A semiconductor memory is provided with means for refreshing the memory. Interrupt requests generated by the memory initiate refreshing cycles, which take place in parallel with normal read/write memory operations. The memory is divided in two parts or blocks. If the central processor unit assigns a cycle for read/write operation to one of the two blocks, the same cycle is utilized to recharge or refresh a row of storage elements of the integrated units which constitute the other block of the memory. Refreshing is regulated by low priority interrupt requests and, if not responded to, by high priority interrupt requests, which are mandatory.

Abstract: A circuit for energizing the electromagnet of the print head of a high speed impact printer, wherein such circuit operates effectively with an unregulated supply voltage by providing energization current pulses whose level and duration are dependent on the present level of such supply voltage.

Abstract: Apparatus for the flexible coupling of peripheral units to a digital computer system, wherein any input/output port of the system is capable of communicating with a peripheral unit over various forms of interface.

Abstract: A dynamic current limiting circuit to be used in connection with voltage regulators of the switching type is provided. The current limiter consists of electronic means suitably connected into the power stage of a conventional switching voltage regulator, for the purpose of reducing or removing the detrimental peak current spikes which occur whenever the power transistor switches from the non-conducting to the conducting state.

Abstract: In a tape transport of the type where tape traveling between a pair of tape reels is selectively moved past a recording/readout station by externally controlled capstan means, a novel, semiautomatic system is provided for loading the tape into the transport. In accordance with the present invention, this is accomplished by manual insertion of the tape into a first tape path and by subsequent, stepwise automatic loading into a second tape path when predetermined operating conditions in the transport are present. Transport disabling means, normally operative in the absence of the aforesaid operating conditions, are inhibited during the tape loading operation, becoming operative again when the transport is fully loaded and ready for normal operation. Apparatus for loading tape in this manner avoids the time delays and reliability problems of fully manual loading systems, as well as the high cost and lack of reliability in certain critical areas of fully automatic tape loading equipment.

Abstract: An error voltage signal which is of magnitude related to the difference between the actual speed of a d.c. motor and a desired speed is selectively applied to either the inverting input terminal of an operational amplifier or to its non-inverting input terminal, dependent upon the direction of rotation of the motor. The circuit components connecting the error signal to the input terminals are selected to provide the same absolute value of gain for the amplifier regardless of whether the input is to the inverting terminal or to the non-inverting terminal. The system substantially reduces complexity and diminishes the number of components required for this type of bidirectional speed regulation.

Abstract: A control system for a variable speed peripheral device which is suitable for remote as well as for local connection of the peripheral device to a central processor. For remote connection, the central processor is coupled to the peripheral device by way of a transmission controller, a remote communication line, and the control system connected to the peripheral device. First and second modems terminate the communication line and are connected through standard interfaces to the transmission controller and to the control system respectively. For this connection, the character transmission rate must be lower than, or equal to, the minimum operating speed of the peripheral device. For local connection, the central processor is coupled to the peripheral device by way of the transmission controller, the control system and the standard interface connected thereto.

Abstract: In a data processing system having a plurality of input/output channels, a first plurality of physical resources is dedicated to each of the channels. Said first plurality is sufficient only to enable standard data character exchanges between each of the channels and the central processing unit in a time-sharing manner. A second plurality of physical resources (including registers and logic) is provided which is dedicated to a corresponding plurality of service classes. The service classes are ordered according to a priority criterion and selectively assigned to different channels in accordance with the priority level of the interrupt which has requested the service. In this manner, while services of the same class are not reciprocally interruptible, services of different classes on different channels are hierarchically interruptible.

Abstract: Apparatus for carrying out a set of macroinstructions by means of a microprogram in firmware. The apparatus controls the operating system of a digital computer which is adapted to carry out a set of macroinstructions. The macronistructions are carried out by means of a microprogram in firmware having a fetching phase and an execution phase. Both fetching and execution of macroinstructions are carried out by means of microprograms. One ROM is provided for storing a fetching and execution digital-word, associated with a macroinstruction and contains information relative to each phase respectively. Another ROM is provided for storing the actual microprograms for fetching and executing macroinstructions respectively.

Abstract: Apparatus for providing notification of and distinguishing among various kinds of errors in information transferred between the central processor and the peripheral units of a digital computer system by isolating the elements of such system in which certain kinds of errors can occur.

Abstract: A semiconductor memory includes means for separating the causes of error affecting the addressing and recording of information bits from those affecting check, or parity, bits. The recording words comprise 16 information bits, and are divided into two "bytes", of eight bits each. Each byte is provided with its own check bit; and two half-words of nine bits are recorded at the same address. Each submodule of the memory comprises two printed-circuit cards. The first card supports the integrated memory units wherein, for each word, the information bits of the first byte and the check bit of the second byte are recorded; the second card supports the memory units wherein the information bits of the second byte and the check bit of the first byte are recorded.

Abstract: A magnetic recording and reproducing head is provided for use in cassette applications. The head comprises a pair of tracks and is constructed such that the reading gap assigned to the first track is aligned with the recording and erasing gap assigned to the other track, the tracks being arranged reciprocally.

Abstract: This disclosure relates to a guidance arrangement for web handler, for example of the type used for moving an elongated tape. A direction modifying idler roller has associated therewith means for maintaining the alignment of a tape with tape receiving and dispensing members disposed on opposite sides of the roller irrespective of any misalignment of the roller. Basically, the tape guidance means includes a fixed member having arcuate tape guide surfaces over which the tape slides and each guide surface having associated therewith shoulders which are resiliently mounted and which engage opposite edges of the tape.