Abstract: A method for recognizing and extracting named entities in a natural language input text processing comprising: performing, by a compressed named entities recognition (NER)-model-based named entity recognizer, a first stage NER on the input text to generate a first stage determination of whether at least one named entity exists in the input text; if the first stage NER determines no named entity exists in the input text, performing, by a rule based named entity recognizer, a second stage NER on the input text to generate a second stage NER result; if the first stage NER determines at least one named entity exists in the input text, generating, by the compressed NER-model-based named entity recognizer, a first stage NER result; and integrating, by a NER result integrator, the first stage NER result and the second stage NER result to generate a final NER result.

Abstract: A segmented 3D multi-view image generator generates fewer multi-view view images for partitions having less salient features. Saliency values are calculated based on a depth map and image processing of the input image. The saliency values are compared to thresholds to map pixel locations to first, second, and third partitions. First, second, and third segmented images are created from the input image using a partition map. A multi-view generator uses the depth map and viewer eye locations to generates 28 view images from the first segmented image, 14 unique view images from the second segmented image that are replicated to 28 view images, and 7 unique view images from the third segmented image that are replicated to 28 view images. The view images for each segment are interlaced to generated interlaced segmented images that are then integrated together into a single 3D image that drives a 28-view autostereoscopic display.

Abstract: A method for setting-up a tunnel connection for transporting data packets over a high latency network connection in a communication network comprises the step of, at a module or node configured on a tunnel connection initiator side of the high latency network connection, using a non-TCP connection to encapsulate a set-up connection message for sending to a module or node configured on a core network (CN) side of the backhaul network to offset-up a data packet transport tunnel connection between the initiator side of the high latency network connection and core network (CN) side of the high latency network connection.

Abstract: Described is a controller for a DC/DC converter of a type having N power stages, where N is a natural number greater or equal to 2. The controller comprises a decision maker module, a proportional-integral-derivative (PID) or proportional-integral (PI) control module and a transient compression control module. The decision maker module determines a first steady state mode of operation and a second transient mode of operation and is configured to switch control between said first steady state mode of operation to said second transient mode of operation when an operating parameter of one of the N power stages exhibits a predetermined operating condition relative to a predetermined operating limit and/or a predetermined, calculated or selected threshold. The PID or PI module regulates the operating parameter during said first steady state mode of operation.

Abstract: A low-core-loss transformer for high transfer ratio and high power density applications can have five pillars including four corner pillars and at least one center pillar between magnetic metal plates. The center pillar provides an additional flux path to reduce thermal and core losses and improve efficiency. Magnetic flux density may be further reduced by having multiple central pillars in an N-track configuration in several kinds of symmetrical arrangements. The low-core-loss transformer achieves a flexible voltage transfer ratio. The ratio can be either even or odd numbers. An odd ratio design is able to fulfill the requirement of future data centers to supply a 400-volt high-distribution power bus. The transformer windings can be traces on a Printed Circuit Board (PCB) that integrate electronic components for a compact and modular design.

Abstract: A receiver is energized by wireless power from a coil antenna. A matching network tunes the receiver to a resonant frequency and a bridge and capacitor generate an output voltage. The output voltage is divided and compared to a reference voltage. An asynchronous digital controller increases a digital count when the compare result is true, but decreases the digital count when the compare result is false. A current-steering Digital-to-Analog Converter (DAC) shunts a current from the output that is a function of the digital count. The asynchronous digital controller, comparator, and DAC do not use a system clock, so the digital feedback to the shunt current operates when the target output voltage is reached, preventing over-voltage when waiting for the system clock to begin pulsing. The digital count is compared to a digital threshold to recover transmitted Amplitude-Shifted-Keyed (ASK) data.

Abstract: A method for character recognition and semantic for natural language processing comprising extracting a sequence of feature vectors from a sequence of input character images by a convolutional neural network (CNN) feature extractor. The sequence of feature vectors comprises a plurality of feature vectors, each feature vector representing an approximate-match of its corresponding input character in the sequence of input character images. The method further comprises applying a sequential classifier sequentially as a sliding window of a size of a plurality consecutive feature vectors upon the sequence of feature vectors from a first feature vector in the sequence of feature vectors to the last feature vector in the sequence of feature vectors; and recognizing an output character for a targeted feature vector among the applied-upon consecutive feature vectors within the sliding window as it is sliding across the sequence of feature vectors.

Abstract: A synchronizer generates cross-products of In-phase (I) and Quadrature (Q) samples and stores the sign bits for the sine and cosine cross-products. The sign bits are compared to a local reference of a frame-start bit-sequence and the compare results accumulated as I and Q correlations for symbol and half-symbol sampling. Linear combinations of the accumulated I and Q correlations for the symbol and half-symbol sampling generate linear combination results for frequency bins that peak at a different implied Carrier Frequency Offset (CFO) settings. The maximum of the linear combination results is selected and the implied CFO setting for that frequency bin is applied to a demodulator to adjust the receiver's CFO setting and bit synchronization. Computational complexity is reduced since only the sign bit of each cross-product is retained for correlation with the frame-start bit-sequence. Linear combinations can support a wide CFO range.

Abstract: A power device package includes a substrate, a high side power device, a low side power device and a driver device. The substrate includes a top surface, a bottom surface and a plurality of vias that extend through the substrate. The high side and low side power devices are disposed on the top surface of the substrate and connected with each other. The driver device is disposed on the bottom surface of the substrate and electrically connected with the high side and low side power devices through the vias to drive the high side and low side power devices in response to a control signal. The distance between the driver device and the high side and low side power devices is determined by the thickness of the substrate such that that a parasitic inductance between the driver device and the high side power device or the low side power device is reduced.

Abstract: A shielded Schottky heterojunction power transistor is made from a Silicon-Carbide (SiC) wafer with SiC epitaxial layers including a N+ source and a Silicon N-epitaxial layer under the gate with higher channel mobility than SiC. The bulk of the wafer is a N+ SiC drain contacted by backside metal. A trench is formed between heterojunction transistors. Metal contacting the N+ source is extended into the trench to form a Schottky diode with the N-SiC substrate. P+ taps on the sides of the trench connect the metal to a P-SiC body diode under the heterojunction gate, and also prevent the Schottky metal from directly contacting the P body diode. Buried P pillars with P+ pillar caps are formed under the trench Schottky diode and under the heterojunction transistors. The P pillars provide shielding by balancing charge with the N substrate, acting as dielectrics to reduce the E-field above the pillars.

Abstract: A panoramic video stream is compressed. Sinusoidal projection is performed on spherical input images to generate pseudo-cylindrical projection images. A lower-left region and a lower-right region of the image are cut and moved to upper corners of the rectangular bounding box around the pseudo-cylindrical projection image. These upper corners are non-effective areas of default dark pixels with no image pixels. A bottom one-third of the rows of pixels from the image that contained the moved regions are deleted, compressing the image by 33%. Default dark pixels in interface regions between the moved regions and the pseudo-cylindrical projection image are linear interpolated to provide gradual changes in pixel values across the remaining formerly non-effective regions, preventing encoding artifacts caused by abrupt changes in pixel values. Functions may be implemented using lookup tables.

Abstract: A single-temperature-point temperature-sensitivity sensor assumes that all sensitivity lines converge at absolute zero temperature, so during calibration measurement is needed at only one temperature. A sensor output voltage is generated by current from a mirrored current source flowing through a variable resistor. During calibration, the resistance of the variable resistor and the mirror ratio of the mirrored current source are adjusted. An error amplifier compares voltages generated by unit currents generated by unit current sources to adjust the unit current sources and the mirrored current source. Each unit current flows through a grounded-base PNP transistor. A switchable PNP transistor is in parallel with one of the grounded-base PNP transistors and has its base switched on and off to adjust the PNP current for two measurements. The difference between the two measurements is compared to a calibration target to adjust the variable resistor and mirror ratio during calibration at a single temperature.

Abstract: A wireless power transfer system with a class DE inverter for power transfer to a load. The wireless power transfer system includes a half-bridge circuit, a zero voltage switching (ZVS) tank, a shunt capacitor array, an evaluation circuit, and a controller. The half-bridge circuit has two transistors connected in series with each of the two transistors driven by a gate driving signal with a duty cycle. The ZVS tank and the shunt capacitor array are electrically connected with the half-bridge circuit. The ZVS tank includes two capacitors and an inductor. The shunt capacitor array has a capacitance that is tunable. The evaluation circuit calculates a power conversion efficiency of the system. The controller receives the power conversion efficiency from the evaluation circuit and generates control signals to adjust the duty cycle of the gate driving signal and to adjust the capacitance of the shunt capacitor array in order to maximize the power conversion efficiency of the system.

Abstract: The invention provides an apparatus for inspecting a light transmissible optical component. The apparatus comprises an image capturing module arranged on a first side of a support configured to hold a light transmissible optical component whilst it is being inspected. The apparatus includes an illumination device configured to shape light from a light source and to illuminate a selected portion of a surface of said light transmissible optical component with said shaped light to enable the image capturing module to capture any of a bright field image, a dark field image, or a combined bright field and dark field image of the light transmissible optical component being held by the support.

Abstract: A method of generating an electronic 3D walkthrough environment of a targeted environment, comprising: capturing a panorama at a first location point in the targeted environment; measuring an initial orientation of the camera whenever a panorama is captured; moving through the targeted environment and at each location point, capturing a live image of surrounding, and measuring an orientation of the camera; determining whether a new panorama is required to be captured at the current location point at where the camera is with the current orientation of the camera, comprising: identifying a sub-image in the panorama last captured that matches the live image captured; and if the sub-image cannot be identified, then a new panorama is required; and generating the electronic 3D walkthrough environment by connecting the panoramas captured.

Abstract: Example embodiment is a power converter that adopt a 3D structure to increase the power density and improve thermal performance. The power converter includes a bottom substrate and at least one side substrate. Both the bottom substrate and the side substrate are rigid. Each side substrate is connected with the bottom substrate by a flexible substrate and forms an angle with the bottom substrate. The bottom substrate is further electrically connected with a plurality of surface mounting devices which are rigid. The flexible substrate provides electrical connection between the bottom substrate and the side substrate.

Abstract: A fully convolutional network (FCN) implemented on a specialized processor optimized for convolution computation can achieve a speed-up in cell classification. Without re-optimizing the specialized processor, a further speed-up is achieved by compacting a testing image of cells, and processing the compacted testing image with the FCN. The testing image is first segmented into a background and regions of interest (ROIs). The ROIs are packed closer together by rearranging the ROIs without resizing them under a constraint that any two adjacent rearranged ROIs are separated by a distance in pixel not less than a minimum distance determined according to stride values of FCN convolutional layers. Geometrical operations in ROI rearrangement include relocating the ROIs and, optionally, rotating the ROIs. The rearranged ROIs are enclosed by a boundary, typically a rectangular boundary, to form the compacted testing image having an area smaller than that of the testing image.

Abstract: A system for detecting a gazing point of a user in a three-dimensional (3D) space based on a virtual screen is provided. The system includes at least a processor and a wearable device, the wearable device further comprising an external camera arranged for capturing images of the user's field of view, and two internal cameras arranged for capturing binocular images of the user's left and right eyes. The processor is designed to determine the gazing point of the user based on a virtual screen. The coordinates of the pupil center as determined according to the images from the internal cameras are mapped to the images from the external camera based on a left and a right mapping relationships, which further mapped to the virtual screen as an intermediate screen for calculating the 3D coordinates of the gazing point.

Abstract: The invention relates to a toy for discharging a liquid. The toy comprises a discharging chamber adapted to receive a liquid from a liquid storage tank; an outlet arranged at the discharging chamber adapted to discharge at least some of the liquid received in the discharging chamber, the outlet being controllable by a covering mechanism movable between a closed position and an open position to thereby close and open the outlet, respectively; a movable member operably connected with the covering mechanism; wherein, in response to a triggering action of the toy, the movable member is movable from a first position to a second position thereby actuating the covering mechanism to move from the closed position to the open position, and at the same time, triggering discharge of the at least some of the liquid from the discharging chamber via the outlet.

Abstract: An Electro-Static-Discharge (ESD) protection device has a Fin Field-Effect Transistor (FinFET) with a silicon fin with a step separating a top fin and a bottom fin. The gate wraps around the top fin but not the bottom fin. Normal gate-controlled channel conduction occurs in the top fin between a source and a drain in the top fin. Underneath the conducting channel is a buried conducting region in the bottom fin that conducts after a breakdown voltage is reached during ESD. A ledge, abrupt slope change in the sidewalls of the fin, or a doping increase occurs at the step between the top fin and bottom fin. The bottom fin is 2-3 times wider than the top fin, causing the resistance of the buried conducting region to be 2-3 times less than the resistance of the conducting channel, steering breakdown current away from the channel, reducing failures during breakdown.