Abstract: Provided is a method of modifying a data path between a user equipment (UE) and a core network node (CNN) in a wireless communication network. The method comprises the steps of: at a network node handling both signalling messages and user data for an existing data path between said UE and said CNN, obtaining data uniquely associated with a data path resource for said UE and/or uniquely identifying said UE and mapping said data to said existing data path; and modifying said existing data path based on said mapping. The network node handling both signal messaging and user data for an existing data path may comprise a gateway (GW) connecting a source base station (SBS) and a target base station (TBS) to a Mobility Management Entity (MME) of the core network, said GW being configured to handle both user plane data and control plane data for a plurality of UEs.

Abstract: A method and a device for image inpainting on arbitrary surfaces in three-dimensional space are described for inpainting a region of a three-dimensional image utilizing a partial differential equation. The method includes obtaining a three-dimensional image on a surface S in three-dimensional space, and each point of the image includes an image point value and a position vector. The method includes locating an inpainting region D and generating an inpainting mask. The method further includes calculating image point values for points inside the inpainting region D and creating a second three-dimensional image to obtain an inpainted image. The present disclosure solves technical problems that previous methods do not work well on three-dimensional images on arbitrary surfaces and improves image inpainting technology.

Abstract: A fully convolutional network (FCN) implemented on a specialized processor optimized for convolution computation can achieve a speed-up in cell classification. Without re-optimizing the specialized processor, a further speed-up is achieved by compacting a testing image of cells, and processing the compacted testing image with the FCN. The testing image is first segmented into a background and regions of interest (ROIs). The ROIs are packed closer together by rearranging the ROIs without resizing them under a constraint that any two adjacent rearranged ROIs are separated by a distance in pixel not less than a minimum distance determined according to stride values of FCN convolutional layers. Geometrical operations in ROI rearrangement include relocating the ROIs and, optionally, rotating the ROIs. The rearranged ROIs are enclosed by a boundary, typically a rectangular boundary, to form the compacted testing image having an area smaller than that of the testing image.

Abstract: A system for detecting a gazing point of a user in a three-dimensional (3D) space based on a virtual screen is provided. The system includes at least a processor and a wearable device, the wearable device further comprising an external camera arranged for capturing images of the user's field of view, and two internal cameras arranged for capturing binocular images of the user's left and right eyes. The processor is designed to determine the gazing point of the user based on a virtual screen. The coordinates of the pupil center as determined according to the images from the internal cameras are mapped to the images from the external camera based on a left and a right mapping relationships, which further mapped to the virtual screen as an intermediate screen for calculating the 3D coordinates of the gazing point.

Abstract: The invention relates to a toy for discharging a liquid. The toy comprises a discharging chamber adapted to receive a liquid from a liquid storage tank; an outlet arranged at the discharging chamber adapted to discharge at least some of the liquid received in the discharging chamber, the outlet being controllable by a covering mechanism movable between a closed position and an open position to thereby close and open the outlet, respectively; a movable member operably connected with the covering mechanism; wherein, in response to a triggering action of the toy, the movable member is movable from a first position to a second position thereby actuating the covering mechanism to move from the closed position to the open position, and at the same time, triggering discharge of the at least some of the liquid from the discharging chamber via the outlet.

Abstract: Methods and systems which provide object edge image representation generation using block based edgel techniques implementing post edgel detection processing to eliminate false edges are described. Embodiments subdivide image data (e.g., image point clouds) to facilitate separate edgel detection processing of a plurality of sub-blocks of the image data. A false edge elimination algorithm of embodiments is applied in recombining the object edge image representation sub-blocks resulting from the sub-block edgel detection processing to eliminate false edge artifacts associated with use of block based edgel detection.

Abstract: An Electro-Static-Discharge (ESD) protection device has a Fin Field-Effect Transistor (FinFET) with a silicon fin with a step separating a top fin and a bottom fin. The gate wraps around the top fin but not the bottom fin. Normal gate-controlled channel conduction occurs in the top fin between a source and a drain in the top fin. Underneath the conducting channel is a buried conducting region in the bottom fin that conducts after a breakdown voltage is reached during ESD. A ledge, abrupt slope change in the sidewalls of the fin, or a doping increase occurs at the step between the top fin and bottom fin. The bottom fin is 2-3 times wider than the top fin, causing the resistance of the buried conducting region to be 2-3 times less than the resistance of the conducting channel, steering breakdown current away from the channel, reducing failures during breakdown.

Abstract: An Electro-Static-Discharge (ESD) input-protection device has an NPNP structure of a N+ cathode formed in a FINFET fin or highly-doped region over a floating P-well, and a P+ fin or highly-doped region anode formed over a floating N-well that touches the floating P-well. The floating P-well is surrounded by an isolating N-well and has a deep N-well underneath to completely isolate the floating P-well from the p-type substrate. No well taps are formed in the floating wells or in the isolating N-wells. The floating P-well and the floating N-well are thus truly floating at all times. Since the wells are floating, the NPNP structure appears as three junction diodes in series, which has a lower capacitance than a single diode that the NPNP structure would appear as when one of the wells was shorted or biased. During an ESD event the NPNP structure behaves as a single diode.

Abstract: An apparatus and method for performing real object detection and control using a Virtual Reality Head Mounted Display System, and more particularly, when the real object detection and control are detecting hand presence and control in free space, in a virtual reality environment, the control being, for example, gestures or movement, in the free space.

Abstract: For an augmented reality (AR) content creation system having a marker database, when a user requests this system to use a first sub-image of an image to update the marker database, this system computes a suitability score of the first sub-image for rating feature richness of the first sub-image and uniqueness thereof against existing markers in the marker database. When the suitability score is less than a threshold value, a second sub-image of the image having a suitability score not less than the threshold value and completely containing the first sub-image is searched. Then the second sub-image, the suitability score thereof and the suitability score of the first sub-image are substantially-immediately presented to the user for real-time suggesting the user to use the second sub-image instead of the first sub-image as a new marker in updating the marker database to increase feature richness or uniqueness of the new marker.

Abstract: Provided is a method and an apparatus for signaling allocation of resources in a joint transmission communication system. The method includes determining one of a plurality of resource allocation schemes to be implemented by two or more of a plurality of transmission points (TPs) comprising a set of coordinated TPs for enabling said two or more of said TPs to transmit data to a scheduled user equipment (UE). The method may comprise determining a bit length of a resource allocation field for a resource allocation signal message based on a number N of resource blocks groups (RBGs) related to a bandwidth of the joint transmission communication system and a number M of TPs comprising said set of coordinated TPs and further include formatting the resource allocation signal message to provide the resource allocation field based on said determined bit length. The resource allocation signal message is transmitted from only one of said set of coordinated TPs to said scheduled UE.

Abstract: A method that prevents overload to input source and reduces parasitic inductance in an inverter circuit with dead-time control. A sensing capacitor senses temperatures of transistors in the inverter circuit. A delay generator changes delay times in response to receiving the temperatures of the transistors from the sensing capacitor. A dead time generation unit changes the dead times for the transistors in response to changes in the delay times.

Abstract: A programmable-threshold power supply selector has two power-supply inputs VDD1 and VDD2. The higher of these two voltages is pre-selected as a common supply that powers all transistors and circuitry in the programmable-threshold power supply selector, including substrates under transistors. An open-loop decision circuit is very stable since it uses no feedback. A tunable voltage divider divides VDD1 by a programmable divisor. The divided VDD1 is compared to a reference voltage to generate switch-control signals. The switch-control signals drive the gates of p-channel switch transistors that connect either VDD1 or VDD2 to an output supply voltage. The different programmable divisor values effectively cause VDD1 to be compared to a programmable threshold voltage VTH. The switch transistors switch the output supply voltage to VDD2 only when VDD1 falls below VTH. The output supply voltage remains at VDD1 even when VDD1 falls below VDD2, eliminating unnecessary power switching.

Abstract: A Quadrature-In, Quadrature-Out (QIQO) clock divider divides by an odd divisor, such as three. An IQ input clock has in-phase and quadrature differential signals. Four stages of dynamic logic are arranged into a loop, with each stage output being one of four IQ output signals that have 90-degree phase separations. Each stage output drives the gates of a p-channel charging transistor and an n-channel discharging transistor of a next stage. Two p-channel charging logic transistors are in series between the next stage output and the p-channel charging transistor, and two n-channel evaluation transistors are in series between the next stage output and the n-channel discharging transistor. Different pairs of the four IQ input clock signals are applied to their gates. When the prior stage output is low, the stage output is charged. When the prior stage output is high, the stage output discharge timing is determined by the IQ signals.

Abstract: Systems and methods which provide for detection of a signal using resource elements in the frequency domain where the signal for which detection is provided is multiplexed with other signals having subcarrier spacing that is different than the signal for which detection is provided are disclosed. Embodiments may provide for detection of a physical random access channel (PRACH) signal in a cellular radio communication system using resource elements in the frequency domain, wherein the PRACH signal is multiplexed with signals of other channels (e.g., data and/or control channel signals) of the cellular radio communication system. A frequency domain filter, such as implementing inverse discrete Fourier transform (IDFT) with down-sampling using indices for PRACH recovery, may be utilized to extract PRACH samples from frequency domain resource elements provided in a resource grid corresponding to a different subcarrier spacing than that of the PRACH.

Abstract: A method and a device for image inpainting on arbitrary surfaces in three-dimensional space are described for inpainting a region of a three-dimensional image utilizing a partial differential equation. The method includes obtaining a three-dimensional image on a surface S in three-dimensional space, and each point of the image includes an image point value and a position vector. The method includes locating an inpainting region D and generating an inpainting mask. The method further includes calculating image point values for points inside the inpainting region D and creating a second three-dimensional image to obtain an inpainted image. The present disclosure solves technical problems that previous methods do not work well on three-dimensional images on arbitrary surfaces and improves image inpainting technology.

Abstract: A silicon carbide chip array containing a silicon carbide substrate; a silicon carbide layer on top of the silicon carbide substrate; a first metal contact connected to the silicon carbide substrate; and two second metal contacts connected to the first portion and the second portion respectively. The silicon carbide layer is thinner and having lower doping than the silicon carbide layer. The silicon carbide layer includes a first portion and a second portion which are separate from each other. Each one of the second metal contacts forms a semiconductor device with the first metal contact. At least one of the first and second portions contains a side face which is inclined with respect to the silicon carbide substrate. Such a configuration enhances the breakdown voltage and reduces leakage current of the resultant silicon carbide diode array.

Abstract: Systems and methods which provide low latency optimization configured to perform from the hardware layer across the operating system to an application. Low latency operation implemented in accordance with embodiments is optimized for a specific application, which interfaces with specific hardware, executing on a host processor-based system configured for low latency optimization according to the concepts herein. For example, a low latency optimization implementation may comprise various modules implemented in both the user space and Kernel space, wherein the modules cooperate to obtain information regarding the services and hardware utilized by an application and to provide such information for facilitating low latency operation with respect to the application.

Abstract: A spatial light modulator (SLM) configured to reduce a fringe field effect (FFE) is provided. The SLM comprises pixels each having a liquid crystal (LC) on a pixel region. At least one pixel is an optimized pixel. The LC of the optimized pixel has an inhomogeneous distribution of pretilt angle or anchoring energy over the pixel region. The inhomogeneous distribution is selected to oppose the FFE. In one embodiment, the optimized pixel is partitioned into an outer region and an interior region. The outer region is an area between the optimized-pixel boundary and a pre-determined distance inwardly therefrom. The inhomogeneous distribution has one value of the pretilt angle or anchoring energy over the outer region and another value over the interior region. In another embodiment, a polymer stabilized network with an inhomogeneous polymerization degree over the pixel region is used to configure the LC layer to oppose the FFE.

Abstract: An integrator in a duty-cycle adjustment circuit has an adjustable charging current provided by a switched current-source array in response to configuration signals from the calibration logic. The integrator's ramp voltage is compared to a threshold voltage by a comparator to generate an output clock. A tunable voltage reference generates a reference voltage that can be tuned by configuration signals from the calibration logic. The reference voltage is divided by a tunable voltage divider, which selects different fractions of the reference voltage for use as the threshold voltage. During calibration, calibration logic repeatedly raises the reference voltage or reduces the charging current from the switched current-source array until a peak voltage of the ramp voltage equals the reference voltage, when a zero duty onset detector detects that the output clock has stopped pulsing. The configuration signals at the zero duty onset condition are stored and used for normal operation.