Abstract: A semiconductor device includes first conductive patterns adjacent to each other and isolated by a trench including first and second trenches, a second conductive pattern formed in the first trench, and an insulating pattern partially filling the second trench under the second conductive pattern and formed between the first conductive patterns and the second conductive pattern.
December 21, 2011
Date of Patent:
January 16, 2018
HYNIX SEMICONDUCTOR INC.
Seung-Jin Yeom, Noh-Jung Kwak, Chang-Heon Park, Sun-Hwan Hwang
Abstract: A combined memory block includes a first memory unit configured to store data and an additional memory unit that forms a stacked structure with the memory unit, wherein the memory unit and the storage unit together form multi-level cells having variable resistance in storing data.
Abstract: An integrated circuit system comprising a first chip including a first period signal generation unit configured to generate a first period signal, transmit a first signal applied from a circuit outside of the integrated circuit system to a second chip, and transmit a second signal transmitted from the second chip to the circuit outside of the integrated circuit system, and the second chip including a second period signal generation unit configured to generate a second period signal, a code generation unit configured to generate codes corresponding to a difference between periods of the first period signal and the second period signal, and a delay unit configured to delay the second signal by using a delay value that is changed according to the codes.
Abstract: A data output circuit includes a main driver including a pull-up driver, coupled between a power supply terminal and a node coupled to the pad and a pull-down driver coupled between the node and a ground terminal, an impedance controller configured to control an output impedance at the node by sensing a voltage at the node and to generate pull-up control signals and pull-down control signals based on the sensed voltage, and a pre-driver configured to control driving strengths of the pull-up driver and the pull-down driver in response to the pull-up control signals, the pull-down control signals, and data.
Abstract: A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer.
May 10, 2012
Date of Patent:
August 30, 2016
Hynix Semiconductor Inc.
Yun-Hyuck Ji, Kwan-Woo Do, Beom-Yong Kim, Seung-Mi Lee, Woo-Young Park
Abstract: An internal voltage compensation circuit is provided which includes a power up signal generator configured to generate a power up signal, a select signal generator configured to compare a level of a first external voltage with a level of a second external voltage to generate first and second select signals, wherein the second select signal is generated in response to the power up signal, and a voltage compensation unit configured to electrically connect an internal voltage to the first external voltage or the second external voltage in response to the first and second select signals.
Abstract: A semiconductor integrated circuit capable of controlling test modes without stopping testing of the semiconductor integrated circuit is presented. The semiconductor integrated circuit includes a test mode control unit configured to produce, in response to address decoding signals, a plurality of test mode signals of a first group and a plurality of test mode signals of a second group. The test mode control unit selectively inactivates the test mode signals of the first group by providing a reset signal using the test mode signals of the second group. Therefore, the testing time of the semiconductor integrated circuit can be reduced by inactivating the previous test mode using the reset signal and by executing a new test mode without disconnecting the test mode state.
Abstract: A method for fabricating a semiconductor device includes forming at least two gate patterns on a substrate, forming sidewalls surrounding the gate patterns, wherein the sidewalls extend above an upper surface of the gate patterns, and forming a first conducting material in a first space and a second space, wherein the first space is provided above the gate patterns and between the sidewalls that extend above the upper surface of the gate patterns and the second space is provided between the gate patterns.
Abstract: A semiconductor device includes an initialization information generation unit configured to operate in response to a first clock and generate first initialization information having a value that is adjusted according to a value of an address signal that corresponds to output data, a domain crossing unit configured to receive the first initialization information in response to the first clock and output the first initialization information as second initialization information by outputting the second initialization information in response to a second clock, and a pulse generation unit configured to operate in response to the second clock and adjust a toggling point in time of a control pulse in response to the second initialization information.
Abstract: A method of operating a memory system according to an aspect of the present disclosure includes storing first data in a memory controller; storing second data in the memory controller, wherein the second data is read from a selected page of a first memory block of a memory device; and performing a program operation for storing third data, that include the first data and the second data, in a selected page of a second memory block of the memory device.
October 25, 2011
Date of Patent:
April 19, 2016
Hynix Semiconductor Inc.
Min Joong Jung, Jung Mi Shin, Wan Seob Lee
Abstract: A semiconductor integrated circuit includes a decoding circuit configured to decode one or more test source signals and generate a plurality of test decoding signals, a transmission circuit configured to transmit the plurality of test decoding signals as a plurality of test mode group signals in response to a test enable signal, wherein the transmission circuit outputs the test mode group signals with maintaining a previous output, when the test decoding signals different from each other are sequentially activated, and a test mode signal output circuit configured to output a plurality of test mode signals corresponding to test mode groups, respectively, in response to the plurality of test mode group signals and one or more test mode select signals.
Abstract: A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed.
Abstract: A method for fabricating a semiconductor device, including forming gate patterns over a substrate, forming conductive layer covering top and sidewalls of each gate pattern, forming a metal layer for a silicidation process over the conductive layer, and silicifying the conductive layer and the gate patterns using the metal layer.
Abstract: A method for operating a non-volatile memory device includes performing an erase operation onto a memory block including a plurality of memory cells, and performing a first soft program operation onto all the memory cells of a string, after the erase operation, grouping word lines of the string into a plurality of word line groups, and performing a second soft program operation onto memory cells coupled with the word lines of each word line group.
Abstract: A semiconductor apparatus is provided. The apparatus includes a transmission control unit configured to generate, in response to a received pulse signal having a first pulse width, transmission control signals with a second pulse width larger than the first pulse width and synchronization control signals with a third pulse width larger than the second pulse width. The apparatus also includes a reception control unit configured to generate reception control signals in response to the synchronization control signals.
Abstract: A semiconductor device and a method for fabricating the same are provided to enable a bit line to be formed easily, increase a bit line process margin and reduce capacitance between the adjacent bit lines. The semiconductor device comprises: a first pillar and a second pillar each extended vertically from a semiconductor substrate and including a vertical channel region; a first bit line located in the lower portion of the vertical channel region inside the first pillar and the second pillar; and an interlayer insulating film located between the first pillar and the second pillar that include the first bit line.
Abstract: A semiconductor device and a method of fabricating the same are provided, in which a full overlap between a storage node contact and an active region to solve an overlay in an etching process and an etching width of a storage node is increased to improve a processing margin. The semiconductor device includes a main gate and a device isolation structure disposed in a semiconductor device, an isolation pattern disposed over the device isolation structure, and contact plugs disposed at each side of the isolation pattern.
Abstract: An electrostatic discharge protection device includes first and second wells of a first conductivity type, the first and second wells having different impurity doping concentrations, respectively, a gate formed on the first well, a source region of a second conductivity type formed at one side of the gate in the first well, a drift region of the second conductivity type formed at the other side of gate and over both of the first well and the second well, and a drain region of the second conductivity type formed in the drift region of the second well.
Abstract: A semiconductor device includes a memory block including a transistor region and a memory region. A variable resistance layer of the memory region acts as a gate insulating layer in the transistor region.
Abstract: A non-volatile memory device includes a plurality of bit lines; a plurality of page buffers corresponding to the bit lines, respectively, and configured to each store a write data; and a control circuit configured to control at least one page buffer of the plurality of page buffers to store the write data of a first logic level and control other ones of the plurality of page buffers to store the write data of a second logic level, wherein the control circuit is further configured to select the at least one page buffer based on an address inputted to the control circuit. Since write data of diverse patterns may be generated within a non-volatile memory device by using a portion of the bits of the address, a test operation of the non-volatile memory device may be performed within a short time.