Abstract: A non-volatile memory device includes a plurality of bit lines; a plurality of page buffers corresponding to the bit lines, respectively, and configured to each store a write data; and a control circuit configured to control at least one page buffer of the plurality of page buffers to store the write data of a first logic level and control other ones of the plurality of page buffers to store the write data of a second logic level, wherein the control circuit is further configured to select the at least one page buffer based on an address inputted to the control circuit. Since write data of diverse patterns may be generated within a non-volatile memory device by using a portion of the bits of the address, a test operation of the non-volatile memory device may be performed within a short time.

Abstract: A phase change random access memory device includes a bottom electrode contact formed within a bottom electrode contact hole, a phase-change material pattern formed to surround a side of an upper portion of the bottom electrode contact, and an insulating layer buried within the phase-change material pattern and formed on an upper surface of the bottom electrode contact.

Abstract: A semiconductor device is disclosed, which reduces the depth of a metal contact so that an etching margin is increased in forming a contact hole. In addition, the semiconductor device and the method for forming the same increase a contact area between a plate electrode and a metal contact so that a power source can be more easily provided to the plate electrode. Thus, a sensing noise is reduced and a process margin is improved, resulting in improvement of device operation characteristics.

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor memory device. A contact plug is formed by wet etching. An aspect ratio of SAC is decreased and SAC fail is reduced so that a process margin is secured. The semiconductor device includes a semiconductor substrate comprising an active region and a device isolation layer defining the active region, a conductive pattern formed on the semiconductor substrate, and a nitride layer formed on the semiconductor substrate perpendicularly to the conductive pattern.

Abstract: A variable resistive memory device includes an array of a plurality of memory cells. Each of the plurality of memory cells includes first and second electrodes, and an SbmSen material layer (where m and n are positive numbers, respectively) interposed between the first electrode and the second electrode. The SbmSen material layer includes a separation structure in which a plurality of Sb atoms are in contact with a plurality of Se atoms.

Abstract: A page buffer circuit includes first and second bit lines coupled to a first sensing circuit and with a first space therebetween, and third and fourth bit lines coupled to a second sensing circuit and with the first space therebetween. The second bit line and the third bit line are adjacent to each other with a second space therebetween, and the second space is smaller than the first space.

Abstract: A read method of a semiconductor memory device includes performing a read operation on target cells by using a first read voltage, terminating the read operation on the target cells if, as a result of the read operation on the target cells, error correction is feasible, performing a read operation on first cells next to the target cells along a first direction if, as a result of the read operation on the target cells, error correction is unfeasible, performing the read operation again on the target cells by selecting one of a plurality of read voltages in response to a result of the read operation on the first cells and by using the selected read voltage for reading data of the target cells, and terminating the read operation on the target cells if error correction is feasible.

Abstract: Semiconductor memory device with high-speed data transmission capability, system having the same includes a plurality of address input circuits and a plurality of data output circuits and a training driver configured to distribute address information input through the plurality of address input circuits together with a data loading signal for a read training, and generate data training patterns to be output through the plurality of data output circuits.

Abstract: A data transferring circuit includes a data transferor configured to transfer data through a plurality of parallel data transfer lines, wherein the data transferor is further configured to partially invert the transferred data in response to an inversion signal, and a pattern sensor configured to enable the inversion signal when data transferred through the parallel data transfer lines is to cause three sequential lines to transfer data of a logic value through a middle one of the sequential lines and data of an inverse of the logic value through the remaining ones of the sequential lines or cause all of the transfer lines to transfer data of a same logic value.

Abstract: A semiconductor device includes a supplementary layer and a silicon layer stacked over a substrate, a trench penetrating the supplementary layer and the silicon layer and formed over the substrate, a gate insulation layer formed along a surface of the trench, and a buried gate formed over the gate insulation layer and filling a portion of the trench.

Abstract: A redundancy circuit includes a plurality of block address lines, a first fuse array storing a first data, a plurality of first local lines configured to supply a verification voltage to the first fuse array in response to a signal of a corresponding line among the plurality of block address lines, a second fuse array storing a second data, a plurality of second local lines configured to supply the verification voltage to the second fuse array in response to a signal of a corresponding line among the plurality of block address lines, and a plurality of verification lines configured to check the first data of the first fuse array and the second data of the second fuse array, wherein the plurality of verification lines are shared by the first fuse array and the second fuse array and are disposed between the first fuse array and the second fuse array.

Abstract: A method for manufacturing a semiconductor device includes forming plural layers of a MTJ device, depositing a conductive layer over the plural layers, forming a hard mask pattern used for patterning the plural layers over the conductive layer, where the conductive layer is exposed through the hard mask pattern, performing hydrogen peroxide process to volatilize the exposed conductive layer and removing the volatilized conductive layer, and patterning the plural layers by using the hard mask pattern as an etch mask to form the MTJ device.

Abstract: An on die thermal sensor (ODTS) of a semiconductor memory device includes a high voltage generating unit for generating a high voltage having a voltage level higher than that of a power supply voltage of the semiconductor memory device; and a thermal information output unit for sensing and outputting a temperature as a thermal information code, wherein the thermal information output unit uses the high voltage as its driving voltage.

Abstract: An image sensor includes first impurity regions formed in a substrate, second impurity regions formed in the first impurity regions, wherein the second impurity regions has a junction with the first impurity regions, recess patterns formed over the first impurity regions in contact with the second impurity regions, and transfer gates filling the recess patterns.

Abstract: A semiconductor memory device includes a bit line sense amplification unit configured to sense/amplify data loaded on a bit line, and a driving control unit configured to supply a power line of the bit line sense amplification unit with an overdriving voltage in an overdriving period and supply an internal voltage line with a voltage of the power line of the bit line sense amplification unit in a discharge driving period.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed, which can form a gate electrode material only in a recess of a buried gate cell structure, improve a Gate Induced Drain Leakage (GIDL) of a gate electrode material and a junction (i.e., drain region), prevent the gate electrode material from overlapping with the junction (i.e., drain region), and adjust the depth of junction, thereby improving channel resistance. The method for manufacturing a semiconductor device includes forming a device isolation region defining an active region over a semiconductor substrate, burying a gate electrode material in the semiconductor substrate, forming a gate electrode pattern by etching the gate electrode material, wherein the gate electrode pattern is formed at sidewalls of the active region including a source region, and forming a capping layer in the exposed active region.

Abstract: An apparatus for processing an image in a digital camera includes an image signal collection unit configured to process an image collected from a lens into image information using a CMOS image sensor (CIS), and an image correction unit configured to compensate for an intensity in response to a compensation curve corresponding to the image information collected by the image signal collection unit and output an image signal compensated depending on the intensity.

Abstract: An internal voltage generation circuit includes a plurality of active driving units configured to supply a plurality of active power supply voltages to a plurality of voltage terminals, respectively, in an active mode, and a common standby driving unit configured to commonly supply a standby power supply voltage to the plurality of voltage terminals in a standby mode.

Abstract: A nonvolatile memory device includes a pipe gate having a pipe channel hole; a plurality of interlayer insulation layers and a plurality of gate electrodes alternately stacked over the pipe gate; a pair of columnar cell channels passing through the interlayer insulation layers and the gate electrodes and coupling a pipe channel formed in the pile channel hole; a first blocking layer and a charge trapping and charge storage layer formed on sidewalls of the columnar cell channels; and a second blocking layer formed between the first blocking layer and the plurality of gate electrodes.

Abstract: A semiconductor memory device includes a delay locked loop configured to generate a delay locked loop (DLL) clock signal by delaying an external clock signal by a first delay time and generate a feedback clock signal by delaying the DLL clock signal by the second delay time, wherein the first delay time corresponds to a phase difference between the external clock signal and the feedback clock signal and an output enable control circuit configured to generate an output enable signal in response to CAS latency information and the first and second delay times after the delay locked loop performs a locking operation.