Abstract: A programmable phase shifter is constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ inverter and an RSFQ T flip-flop. A digital word comprising N bits is used to control the amount of phase shift and the phase shifter selectively imparts a respective phase shift for any of 2N states that can be represented by the digital word. The RSFQ logic elements utilize Josephson junctions which operate in the superconducting temperature domain.

Abstract: A superconducting switching amplifier embodying the invention includes superconductive devices responsive to input/control signals for clamping the output of the amplifier to a first voltage or to a second voltage. The amplifier includes a first set of superconducting devices serially connected between a first voltage line and an output terminal and a second set of superconducting devices serially connected between the output terminal and a second voltage line. The first set and the second set of devices are operated in a complementary fashion in response to control signals. When one of the first and second sets is driven to a superconducting (zero resistance) state the other set is driven to a resistive state. In accordance with the invention, the devices of each set are laid out in a pattern and driven in a manner to enable all the devices of each set to be driven to a selected state at substantially the same time.

Abstract: A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays.

Abstract: A superconducting analog-to-digital converter includes a superconducting input loop to which is applied an analog voltage to be converted to a digital format. The superconducting loop includes two Josephson junctions for converting said analog input voltage into a single flux quantum (SFQ) pulse stream having a frequency f1 which is directly proportional to the amplitude of the analog input voltage. The loop includes two outputs for distributing the pulse stream in a cyclical and staggered fashion onto the two loop outputs such that the frequency of the pulses along each one of the loop outputs is f½. Additional frequency divider circuits may be coupled to the loop outputs to produce pulse streams on N output lines having a frequency of f1/N.

Abstract: Routing and distribution of radio-frequency (RF) signals is commonly achieved in the analog domain. However, improved performance and simplified circuit architectures may be obtained by first digitizing the RF signal, and then carrying out all routing in the digital domain. A new generation of scalable digital switches has been developed, which routes both the data and clock signals together, this being necessary to maintain the integrity of the digitized RF signal. Given the extremely high switching speeds necessary for these applications (tens of GHz), this is implemented using Rapid-Single-Flux-Quantum (RSFQ) logic with superconducting integrated circuits. Such a digital switch matrix may be applied to either the receiver or transmitter components of an advanced multi-band, multi-channel digital transceiver system, and is compatible with routing of signals with different clock frequencies simultaneously within the same switch matrix.

Abstract: A system for linearizing the output of a high power amplifier (HPA) designed to transmit an RF modulated signal includes in its transmit section a digital up-converter for processing baseband input signals and generating a desired digital RF waveform, T(s). The desired digital RF waveform T(s) is then fed to a digital predistorter circuit for producing a predistorted digital RF waveform P(s)T(s) which, as modified, may be applied via a high sampling speed high linearity digital to analog converter to the high power amplifier (HPA) to produce an output signal which is a linear function of the baseband input signal. The digital predistorter circuit may be of the adaptive type or of the predictive type. Circuits embodying the invention may include encoding circuitry for converting multi-bit signals to a serial stream of single-bit pulses for enabling simplification in the digital to analog conversion.

Abstract: Routing and distribution of radio-frequency (RF) signals is commonly achieved in the analog domain. However, improved performance and simplified circuit architectures may be obtained by first digitizing the RF signal, and then carrying out all routing in the digital domain. A new generation of scalable digital switches has been developed, which routes both the data and clock signals together, this being necessary to maintain the integrity of the digitized RF signal. Given the extremely high switching speeds necessary for these applications (tens of GHz), this is implemented using Rapid-Single-Flux-Quantum (RSFQ) logic with superconducting integrated circuits. Such a digital switch matrix may be applied to either the receiver or transmitter components of an advanced multi-band, multi-channel digital transceiver system, and is compatible with routing of signals with different clock frequencies simultaneously within the same switch matrix.

Abstract: Digital RF correlation based signal processing arrangements allow for the development of software—controlled radio reception without the need for down-conversion to IF frequencies. Various arrangements are implemented using superconducting RSFQ logic enabling the clock and processing speeds required.

Abstract: A circuit for converting an n-bit number to a serial stream of single-bit pulses includes circuitry for generating n different sets of pulses; each set of pulses corresponding to a bit of the n-bit binary number; the number of pulses in a set of pulses corresponding to a bit “j” being equal to 2(j−1) pulses, where “j” is an integer which varies from one (1) for the LSB to n for the MSB. The circuit also includes n switches each switch having an input port, an output port and a control port. Each different bit is applied to the control port of a switch and the set of pulses corresponding to the bit is applied to the control port of that switch. The output ports of the n switches are coupled to a common point for combining the signals at the output ports and producing a serial stream of single-bit pulses at the common point which is equivalent to the n-bit binary number.

Abstract: The invention provides an analog-to-digital modulator for converting an analog input signal to a digital output signal. The filter is constructed and arranged to subtract the feedback signal from the external input signal and to filter the subtracted signal such that the filter output signal is attenuated when the subtracted signal is outside said pass band. A plurality of superconducting comparators and digital-to-analog converters are utilized in a time-interleaved mode. The feedback loop filter, digital-to-analog converters, and superconducting comparators are arranged within a feedback loop such that the filter output signal from the feedback loop filter is communicated to the superconducting comparators such that the comparators generate Single Flux Quantum pulses- at their digital outputs. The pulses are communicated to the digital-to-analog converters and therein converted to analog signals.

Abstract: Subranging techniques using “digital SQUIDs” are used to design systems with large dynamic range, high resolution and large bandwidth. Analog-to-digital converters (ADCs) embodying the invention include a first SQUID based “coarse” resolution circuit and a second SQUID based “fine” resolution circuit to convert an analog input signal into “coarse” and “fine” digital signals for subsequent processing. In one embodiment, an ADC includes circuitry for supplying an analog input signal to an input coil having at least a first inductive section and a second inductive section. A first superconducting quantum interference device (SQUID) is coupled to the first inductive section and a second SQUID is coupled to the second inductive section.

Abstract: The invention provides a universal, delay-insensitive RSFQ logic cell comprising two input circuits and two clock circuits, each containing a plurality of Josephson elements. The two input circuits generate and sustain persistent currents in response to input currents. The first clock circuit is arranged to be in electrical contact with the first input circuit such that a portion of the SFQ persistent current from the input circuit combines with an SFQ pulse, generated in the clock circuit, to trigger the generation of a SFQ output pulse. The second clock circuit and the second input circuit are connected in a similar manner. The first input circuit is arranged to be in electrical contact with the second input circuit so that a portion of their SFQ currents combine and trigger the generation of a SFQ output pulse. The universal logic cell can be configured to perform various digital/logical functions.

Abstract: One aspect of the invention is directed to on-chip high-frequency, low-jitter clock circuits including long Josephson junction (LJJ) oscillators usable as clock sources. LJJ oscillators embodying the invention may be formed using either “linear” or “annular” long Josephson junctions. This invention enables the generation and distribution of a stable high-frequency on-chip single flux quantum (SFQ) clock. The on-chip clock circuit may include a clock selector circuit and a clock distribution scheme and may be integrated with RSFQ circuits and/or with a wideband analog-to-digital converter (ADC) comparator. The invention also includes a new fluxon “sender” circuit suitable for synchronizing the LJJ oscillator with another oscillator, either on-chip or external to the chip. The new sender circuit may also enable the realization of a novel phase-locked loop (PLL) circuit.

Abstract: The invention relates to a novel antenna which is useful in the manufacture of a bolometer integrated on a silicon chip. An opening in the silicon chip is spanned by two separate thermally, isolated structures. A thin-film antenna, comprising two parts, is located on the structures, with one antenna part on each structure. Radiation received in the larger of the two antenna parts is coupled electromagnetically into the smaller part, where it causes a current to flow. The current is dissipated as heat. A thin-film thermometer measures the temperature rise of the smaller antenna part, due to the dissipated heat. The bolometer achieves improved performance in comparison to previous bolometer designs because the radiation is dissipated in a part of the antenna only, and the bolometer is free from impedance-matching constraints of other designs.

Abstract: A circuit embodying the invention includes two toggle flip-flops formed using Josephson junctions sharing a common inductive element. One flip-flop is responsive to "zero" input signals (IN.phi.) and the other flip-flop is responsive to "one" input signals (IN1). Each flip-flop has two outputs. The two outputs of the flip-flop responsive to IN.phi. may be identified as A.phi. and B.phi. and the two outputs of the flip-flop responsive to IN1 may be identified as A1 and B1. The inductive element is settable to either one of two states by controlling the flow of a bias current therethrough. Depending on the state of current conduction through the inductive element, an IN.phi. input signal will produce an output at either A.phi. or B.phi. and an IN1 input signal will produce an output at either A1 or B1. If, and when, the inductive element is in a first state, an IN.phi. or IN1 input will cause a corresponding output at A.phi.

Abstract: A flat panel display assembly includes an array of micromachined incandescent lamps. According to one aspect of the invention, the array of lamps is placed on a gas filled enclosure to enable the filaments to be operated at higher temperatures with extended lifetimes. According to another aspect of the invention, each lamp (or groups of lamps) may be formed in its own gas filled pocket. In some embodiments, a diode is connected in series with each lamp filament. This arrangement enables the array to be operated such that power is applied to the row (column) at a time and to selected columns. The effective brightness of each lamp may be controlled by determining the length of time each lamp is turned-on.

Abstract: Josephson transmission structures (JTSs) which include Josephson transmission lines (JTLs) with filter circuitry and flux release circuitry. Two or more of these JTSs may be interconnected to form a superconducting high-gain operational amplifier intended for general-purpose analog signal processing is disclosed. The active elements of the amplifier are non-hysteretic Josephson junctions configured as dc SQUIDs (used as flux-to voltage transducers and impedance transformers) and Josephson transmission lines (used as the main source of power gain). The amplifier has inverting and non-inverting voltage inputs, which can be fed from any low-resistance low-voltage sources, including dc SQUIDs. The output of the amplifier is in the form of a voltage which can drive typical transmission line impedances (e.g., 10-100 ohms).

Abstract: An electromagnetic radiation (EMR) responsive detector includes an array of multi-layered cantilevers with each cantilever having at least a first layer for absorbing EMR signals and a second layer for reflecting light incident on the second layer. Each cantilever is formed so it can absorb EMR which gets converted into heat which then causes the cantilever to bend proportionately to the amount of EMR energy it absorbs. The amount of EMR absorbed by each cantilever of the array is optically read-out (sensed) by illuminating the cantilevers of the array and sensing the light reflected from each cantilever. Various schemes for projecting light onto the array and sensing the reflected light are disclosed. The optical read-out of the array eliminates the need for electronic read-out circuitry and accessing wires to be formed on the array.

Abstract: In circuits embodying the invention an analog input signal is magnetically coupled from an input superconducting loop to a second superconducting loop. The analog input signal present in the second loop is magnetically coupled to a third, superconducting comparator, loop in which there is generated current feedback pulses which are magnetically fed back to the second loop to reduce and nullify (i.e., reduce to zero) the magnetic flux and circulating current in the second loop induced by the analog input signal.

Abstract: The invention includes an edge-triggered comparator circuit comprising a first Josephson junction connected between a signal input node and an output node and a sampler network coupled to the output node. The first Josephson junction is part of a low inductance SQUID which exhibits a periodic transfer function whose periodicity is a function of the current injected into the SQUID. The sampler network includes a second Josephson junction connected between a sampling terminal and the output node and a third Josephson junction connected between the output node and a point of reference potential. "N" comparator circuits embodying the invention may be interconnected to form an "N"-bit flash analog-to-digital (A/D) converter. The A/D converter may include an R-2R resistive ladder network connected between an analog signal input terminal and a point of reference potential. The resistive ladder network has N nodes with a different comparator being connected to each node.