Abstract: A reference oscillator controlling device in a Very Small Aperture Terminal (VSAT) for low speed data makes a relatively unstable reference oscillator into a precise reference oscillator by synchronizing the reference oscillator with a clock extracted from a data stream which is generated by a precise reference oscillator in a district center of the VSAT.

Abstract: In accordance of the invention, the Erasable and Programmable Logic Device comprising a test circuit of the input architectures is provided.The test circuit comprises an extra test line 39, a plurality of EPROM transistors 34 having respectively the drain thereof connected to the extra test line and the gate thereof connected to a true input line provided from said one input architecture, sensing means 36 connected to the extra test line for sensing the state of the extra test line, and a buffer circuit 37 connected to the sensing means.

Abstract: A test circuit 2 connected between a programmable "AND" memory array 1 and an Input/Output macrocell 3 in an erasable and programmable logic device, for testing the Input/Output macrocell, comprising, a plurality of bit lines connected to the programmable "AND" memory array and the Input/Output macrocell, a plurality of extra test lines connected to a plurality of exterior pins respectively, a plurality of EPROM(Erasable Programmable Read Only memory) transistors which the drain thereof is connected to the bit line and the gate thereof is connected to the extra test line, wherein the EPROM transistors corresponding to the number of the bit lines connected to one logic sum gate forming a logic sum data path within the Input/Output machrocell are connected to one extra test line, and the other EPROM transistors excepting said EPROM transistors are respectively connected to one bit line and one extra test line.

Abstract: A telephone set capable of selectively accepting callers and enabling partial recognitions of callers is disclosed, and the telephone set includes: tip and ring terminals; a first analogue switch connected to said tip terminal; a first bridge diode connected to the first analogue switch and the ring terminal; a wave rectifying circuit connected to the first bridge diode; a microprocessor connected to the wave rectifying circuit and the first analogue switch; an EEPROM connected to the microprocessor; a hook switch connected to the microprocessor; a selecting switch connected to the microprocessor; a second bridge diode connected to the tip and ring terminals; a hybrid IC circuit connected to the second bridge diode; a DTMF decoder connected to the hybrid IC circuit and the microprocessor; a power supply means for supplying the required power to the internal circuits; and a second analogue switch and a microphone.