Patents Assigned to Ibiden Co., Ltd.
  • Publication number: 20240072322
    Abstract: A heat transfer suppression sheet for a battery pack, the heat transfer suppression sheet being used in a battery pack in which battery cells are connected in series or in parallel and being interposed between the battery cells, the heat transfer suppression sheet containing: a heat-insulating material containing at least one of inorganic particles or inorganic fibers; and a covering material covering at least a part of the heat-insulating material, in which a sealed gap is formed between the heat-insulating material and the covering material, and the covering material is configured such that a communication opening that allows the gap to communicate with the outside of the covering material is formed at a temperature of 60° C. or more.
    Type: Application
    Filed: January 14, 2022
    Publication date: February 29, 2024
    Applicant: IBIDEN CO., LTD.
    Inventors: Hisashi ANDO, Naoki TAKAHASHI
  • Publication number: 20240069068
    Abstract: A conduction inspection jig includes a first member having first openings and a flexural strength of 300 MPa or higher, a second member having second openings and positioned above the first member, a support member positioned between the first member and the second member such that the support member is forming a space between the first member and the second member, and a probe that is positioned in one of the first openings in the first member and one of the second openings in the second member such that the probe penetrates through the one of the first openings, the space formed between the first member and the second member, and the one of the second openings and has a first end portion protruding from the first member and a second end portion protruding from the second member on the opposite side with respect to the first end portion.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 29, 2024
    Applicant: IBIDEN CO., LTD.
    Inventor: Takayuki MORI
  • Patent number: 11917756
    Abstract: A method for manufacturing a printed wiring board includes forming metal posts on a conductor circuit formed on a resin insulating layer, forming the outermost resin layer on the resin insulating layer such that the metal posts is embedded in the outermost resin layer, forming a mask at a dam formation site for a dam structure of the outermost resin layer to surround at least part of a pad group including the metal posts on the outermost resin layer, and reducing a thickness of the outermost resin layer exposed from the mask such that end portions of the metal posts are exposed from the outermost resin layer, that the metal posts form the pad group, and that the outermost resin layer has the dam structure forming part of the outermost resin layer and formed to surround at least part of the pad group including the metal posts.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: February 27, 2024
    Assignee: IBIDEN CO., LTD.
    Inventor: Yuji Ikawa
  • Patent number: 11903128
    Abstract: A wiring substrate includes an insulating layer, a conductor layer formed on a surface of the insulating layer such that the conductor layer includes a conductor pad, and a solder resist layer formed on the surface of the insulating layer such that the solder resist layer is covering the conductor layer and having an opening exposing the conductor pad. The conductor pad of the conductor layer has a substantially rectangular planar shape such that the conductor pads has a main surface, a pair of long sides, a pair of short sides and four corner portions, and the solder resist layer is formed such that the opening is exposing side surfaces at the long sides and 50% or more of the main surface and that the solder resist layer is covering side surfaces at the short sides.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: February 13, 2024
    Assignee: IBIDEN CO., LTD.
    Inventor: Shigeto Iyoda
  • Publication number: 20240049398
    Abstract: A wiring substrate includes an insulating layer, and a conductor layer formed on a surface of the insulating layer and including wiring patterns such that the conductor layer has a polished surface on the opposite side with respect to the insulating layer and includes an upper layer including a plating film and a lower layer including a seed layer for the plating film and directly formed on the surface of the insulating layer. The conductor layer is formed such that a ratio of a thickness of the lower layer to a thickness of the conductor layer is 2.5% or less, the wiring patterns have the minimum wiring width of 5 ?m or less and the minimum inter-wiring distance of 7 ?m or less, and each of the wiring patterns has an aspect ratio in a range of 2.0 to 4.0.
    Type: Application
    Filed: August 4, 2023
    Publication date: February 8, 2024
    Applicant: IBIDEN CO., LTD.
    Inventors: Toshiki FURUTANI, Jun SAKAI
  • Patent number: 11892422
    Abstract: A particulate-matter detecting sensor including an insulating substrate which has a detecting face, detecting conductors formed in the insulating substrate, and a heating section formed on the insulating substrate. Each detecting conductor includes a detecting electrode part, a terminal part, and a connecting part. A portion of the detecting conductor is constituted of a noble metal conductor mainly formed of at least one noble metal selected from Pt, Au, Pd, Rh and Ir. At least a portion of the connecting part is formed of a low expansion conductor mainly formed of a low expansion coefficient metal having linear expansion coefficient lower than that of the noble metal. Both conductors are joined at an overlapping part at which the noble metal conductor and the low expansion conductor are partly overlapped with each other on an insulating layer forming the insulating substrate in a normal line direction of the insulating layer.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: February 6, 2024
    Assignees: IBIDEN CO., LTD., DENSO CORPORATION
    Inventors: Yasutaka Ito, Tomoyoshi Nakamura, Takeshi Ushida, Takehito Kimata, Masahiro Yamamoto
  • Publication number: 20240040692
    Abstract: A printed wiring board includes an insulating layer, a conductor layer formed on the insulating layer, an adhesive layer formed on the conductor layer such that the adhesive layer is covering an upper surface and a side surface of the conductor layer, and a resin insulating layer formed on the insulating layer such that the resin insulating layer is covering the conductor layer formed on the insulating layer. The conductor layer is formed such that the upper surface of the conductor layer has an unevenness having a root mean square roughness Rq of 0.23 ?m or less.
    Type: Application
    Filed: July 25, 2023
    Publication date: February 1, 2024
    Applicant: IBIDEN CO., LTD.
    Inventors: Kentaro WADA, Koji KONDO, Kenji KUNIEDA, Masashi UMETSU, Yuta OKAGA
  • Patent number: 11887767
    Abstract: An inductor built-in substrate includes a core substrate having an opening and a first through hole, a first plating film formed in the first through hole of the core substrate, a magnetic resin body having a second through hole and including a magnetic resin filled in the opening of the core substrate, and a second plating film formed in the second through hole of the magnetic resin body such that the second plating film is formed in contact with the magnetic resin body.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: January 30, 2024
    Assignee: IBIDEN CO., LTD.
    Inventors: Hiroaki Kodama, Atsushi Ishida, Kazuro Nishiwaki
  • Publication number: 20240030144
    Abstract: A wiring substrate includes a first build-up part includes first insulating layers, first conductor layers and first via conductors, and a second build-up part laminated to the first build-up part and including second insulating layers, second conductor layers and second via conductors. The first conductor layers in the first build-up part and the second conductor layers in the second build-up part include wirings such that a wiring width and an inter-wiring distance of the wirings in the first conductor layers are smaller than a wiring width and an inter-wiring distance of the wirings in the second conductor layers, an aspect ratio of the wirings in the first conductor layers is in the range of 2.0 to 4.0, the wiring width of the wirings in the first conductor layers is 3 ?m or less, and the inter-wiring distance of the wirings in the first conductor layers is 3 ?m or less.
    Type: Application
    Filed: July 24, 2023
    Publication date: January 25, 2024
    Applicant: IBIDEN CO., LTD.
    Inventors: Toshiki FURUTANI, Masashi KUWABARA
  • Patent number: 11882656
    Abstract: A wiring substrate includes a first conductor layer, an insulating layer formed on the first conductor layer, a second conductor layer formed on the insulating layer, a connection conductor penetrating through the insulating layer and connecting the first and second conductor layers, and a coating film formed on a surface of the first conductor layer and adhering the first conductor layer and the insulating layer. The first conductor layer includes a conductor pad in contact with the connection conductor such that the conductor pad has a surface having a first region and a second region on second conductor layer side and that surface roughness of the first region is different from surface roughness of the second region, and the conductor pad of the first conductor layer is formed such that the first region is covered by the coating film and that the second region is covered by the connection conductor.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: January 23, 2024
    Assignee: IBIDEN CO., LTD.
    Inventors: Takema Adachi, Daisuke Minoura
  • Publication number: 20240023250
    Abstract: A wiring substrate includes a core substrate; a first build-up part including first conductor layers, a second build-up part including second conductor layers, a third build-up part including third conductor layers and having the outermost surface of the wiring substrate, and a fourth build-up part including one or more fourth conductor layers and having the outermost surface of the wiring substrate. The minimum wiring width of wirings in the third conductor layers is smaller than that of wirings in the first, second and fourth conductor layers. The minimum inter-wiring distance of the wirings in the third conductor layers is smaller than that of the wirings in the first, second and fourth conductor layers. The wirings in the third conductor layers have the minimum wiring width of 3 ?m or less, the minimum inter-wiring distance of 3 ?m or less, and an aspect ratio in the range of 2.0 to 4.0.
    Type: Application
    Filed: July 12, 2023
    Publication date: January 18, 2024
    Applicant: IBIDEN CO., LTD.
    Inventors: Toshiki FURUTANI, Masashi KUWABARA
  • Publication number: 20240018889
    Abstract: A mat material having a sufficiently high initial compression surface pressure is provided. The mat material of the present disclosure includes inorganic fibers; and an inorganic binder and an organic binder attached to the inorganic fibers, wherein the mat material has an initial compression surface pressure of 900 kPa or more as measured when compressed to a bulk density of 0.50 g/cm3.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 18, 2024
    Applicant: IBIDEN CO., LTD.
    Inventors: Toshiyuki MAEDA, Takayuki KAWABE
  • Publication number: 20240021532
    Abstract: A wiring substrate includes insulating layers, conductor layers formed on the insulating layers, and via conductors formed in the insulating layers such that the via conductors are connecting the conductor layers through the insulating layers. The conductor layers include a first conductor layer and the outermost conductor layer formed such that the outermost conductor layer includes first conductor pads positioned to mount a first component and second conductor pads positioned to mount a second component and that the first conductor layer includes wiring patterns including first wiring patterns connecting the first conductor pads and second conductor pads, and the first conductor layer in the conductor layers is formed such that the wiring patterns have the minimum wiring width of 3 ?m or less, the minimum inter-wiring distance of 3 ?m or less and an aspect ratio in the range of 2.0 to 4.0.
    Type: Application
    Filed: July 13, 2023
    Publication date: January 18, 2024
    Applicant: IBIDEN CO., LTD.
    Inventors: Toshiki FURUTANI, Masashi KUWABARA
  • Patent number: 11871515
    Abstract: A wiring substrate includes an insulating layer having a through hole, a first conductor layer formed on a first surface of the insulating layer, a second conductor layer formed on a second surface of the insulating layer, an interlayer connection conductor formed in the through hole such that the interlayer connection conductor is connecting the first and second conductor layers, and a resin body formed in the through hole of the insulating layer such that a volume occupancy rate of the resin body is in a range of 30% to 55% in the through hole. The interlayer connection conductor is formed such that the interlayer connection conductor has a length in a range of 1000 ?m to 2000 ?m in a thickness direction of the insulating layer and that a volume occupancy rate of the interlayer connection conductor is in a range of 45% to 70% in the through hole.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: January 9, 2024
    Assignee: IBIDEN CO., LTD.
    Inventors: Yasuki Kimishima, Satoru Kawai
  • Patent number: 11866378
    Abstract: Disclosed is a method for manufacturing a honeycomb structure. The method includes molding a molded body from a mixture containing silicon carbide particles, an organic component, and a dispersion medium, removing the organic component included in the molded body to obtain a porous honeycomb body, and impregnating an inner portion of partition walls of the porous honeycomb body with metal silicon. In a state in which the porous honeycomb body is placed on a support inside a container containing solid metal silicon, the impregnating an inner portion of the partition walls is performed by heating the inside of the container to a temperature higher than or equal to a melting point of the metal silicon so that the porous honeycomb body is impregnated with molten metal silicon through the support that is porous.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: January 9, 2024
    Assignee: IBIDEN CO., LTD.
    Inventors: Sonosuke Ishiguro, Yoshihiro Koga
  • Publication number: 20240008176
    Abstract: A wiring substrate includes a core substrate, a first build-up part formed on a first surface of the substrate and including insulating layers and conductor layers, and a second build-up part formed on a second surface of the substate on the opposite side with respect to the first surface and including insulating layers and conductor layers. The first build-up part includes a first region and a second region such that a distance between adjacent conductor layers in the second region is smaller than a distance between adjacent conductor layers in the first region, the conductor layers in the second region include second wirings having the minimum wiring width and the minimum inter-wiring distance that are smaller than the minimum wiring width and the minimum inter-wiring distance of first wirings of the conductor layers in the first region and the insulating layers are continuous in the first region and second region.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 4, 2024
    Applicant: IBIDEN CO., LTD.
    Inventor: Toshiki FURUTANI
  • Publication number: 20240008191
    Abstract: A wiring substrate includes a first insulating layer, a conductor layer formed on the first insulating layer and including a wiring pattern, an organic coating film formed on the conductor layer such that the organic coating film is formed on the wiring pattern of the conductor layer, and a second insulating layer formed on the first insulating layer such that the second insulating layer is covering the conductor layer. The conductor layer is formed such that the wiring pattern has a polished surface on the opposite side with respect to the first insulating layer, and the organic coating film is formed on the wiring pattern of the conductor layer such that the organic coating film is covering the polished surface of the wiring pattern.
    Type: Application
    Filed: June 28, 2023
    Publication date: January 4, 2024
    Applicant: IBIDEN CO., LTD.
    Inventor: Toshiki FURUTANI
  • Publication number: 20230422408
    Abstract: A printed wiring board includes a first conductor layer, a resin insulating layer having an opening extending from a first surface to a second surface of the resin insulating layer and laminated on the first conductor layer, a second conductor layer formed on the first surface of the resin insulating layer such that the first conductor layer is facing the second surface of the resin insulating layer on the opposite side with respect to the first surface, and a via conductor formed in the opening of the resin insulating layer such that the via conductor is connecting the first conductor layer and the second conductor layer and that the via conductor and the second conductor layer include a seed layer and an electrolytic plating layer formed on the seed layer. The seed layer includes an amorphous metal in a range of 5 wt % to 80 wt %.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 28, 2023
    Applicant: IBIDEN CO., LTD.
    Inventors: Jun SAKAI, Kyohei YOSHIKAWA
  • Publication number: 20230422406
    Abstract: A printed wiring board includes an insulating layer, a conductor layer formed on the insulating layer and including one or more conductor circuits, an insulating adhesive layer covering a surface of the conductor layer and a part or parts of the insulating layer exposed from the conductor layer, and a resin insulating layer formed on the insulating layer and the conductor layer such that the insulating adhesive layer is sandwiched between the conductor layer and the resin insulating layer. The insulating adhesive layer includes a first portion covering an upper surface of the one or more conductor circuits and a second portion covering a side surface of the one or more conductor circuits and a thickness of the first portion is greater than a thickness of the second portion.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 28, 2023
    Applicant: IBIDEN CO., LTD.
    Inventor: Takuya INISHI
  • Patent number: 11856699
    Abstract: An inductor built-in substrate includes a core substrate having openings and first through holes formed therein, a magnetic resin filling the openings and having second through holes formed therein, first through-hole conductors formed in the first through holes respectively such that each of the first through-hole conductors includes an electroless plating film and an electrolytic plating film, and second through-hole conductors formed in the second through holes respectively such that each of the second through-hole conductors includes an electroless plating film and an electrolytic plating film. The first through-hole conductors and the second through-hole conductors are formed such that a thickness of the electroless plating film in the first through-hole conductors is larger than a thickness of the electroless plating film in the second through-hole conductors.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: December 26, 2023
    Assignee: IBIDEN CO., LTD.
    Inventors: Satoru Kawai, Yasuki Kimishima