Abstract: In one aspect, an ion beam profiler for use in an ion implanter is disclosed that includes a Faraday cup disposed in an end-station of the ion implanter in a path of an ion beam traveling from a source to the end-station. The Faraday cup comprises an aperture that is adapted to allow passage of a cross-sectional slices of the beam. An array of ion detectors is disposed behind the Faraday cup in substantial register with the aperture so as to receive different slices of the beam as the beam is scanned across the aperture. The bean profiler further comprises an analyzer that is coupled to the detector array for analyzing detector signals generated in response to ion impingement so as to compute a two-dimensional cross-sectional profile of the beam.

Abstract: The present invention provides methods for forming SOI wafers having internal gettering layers for sequestering metallic impurities. More particularly, in one embodiment of the invention, a plurality of sites for sequestering metallic impurities are formed in a silicon substrate by implanting a selected dose of oxygen ions therein. In one embodiment, an epitaxial layer of crystalline silicon is formed over the substrate, and a buried continuous oxide layer is generated in the epitaxial layer, for example, by employing a SIMOX process.

Abstract: Wafer-holding structures formed from thermosetting resins are disclosed for use in semiconductor processing including, for example, SIMOX wafer processing. At least a portion of the distal portion of the holder comprises graphite, thereby reducing wafer rotation during implantation while maintaining the desired overall thermal signature provided by the thermosetting resin. In one embodiment a pin is disclosed that is adapted to receive a wafer edge, and is coupled with a wafer holder assembly. The pin can be filled with a conductive material to provide an electrical pathway between the wafer and the wafer holder assembly, which can be coupled to a ground. This arrangement provides a conductive path for inhibiting electrical discharges from the wafer during the ion implantation process. The pin exhibits thermal isolation characteristics and sufficient hardness so as to not effect localized thermal dissipation of the wafer, yet is sufficiently soft so as to not mark or otherwise damage the wafer.

Abstract: In one aspect, the present invention provides a method for characterizing a (scanned) ion beam pattern. In one embodiment, the method includes providing a semiconductor calibration wafer having a buried ion implanted region with a known profile, exposing the calibration wafer to the (scanned) ion beam to implant a dose of ions therein so as to augment the ion implanted region, measuring a profile of the augmented region, e.g. along a specific diameter aligned with the (scanning) axis of the ion beam pattern under measurement, and characterizing the (scanned) ion beam pattern by comparing the measured profile of the augmented region with the known profile of the calibration region.

Abstract: Methods and apparatus are disclosed for removing particles from an ion implantation chamber by introducing at least one sacrificial wafer into the implanter and subjecting it to ion implantation. As the sacrificial wafer is exposed to the ion beam, it becomes charged. Particles present in the implantation chamber are then drawn to a charged wafer surface by electrostatic forces. The sacrificial wafer thus serves as a gettering element, attracting and capturing particulates from the surrounding environment.

Abstract: The present invention provides a method for generating silicon-on-insulator (SOI) wafers that exhibit a high electrical resistivity. In one embodiment of a method according to the teachings of the invention, a SIMOX process is sandwiched between two Full Oxygen Precipitation (FOP) cycles that sequester interstitial oxygen present in the substrate in the form of oxide precipitates, thereby enhancing the electrical resistivity of the susbtrate.

Abstract: The present invention provides methods and system for forming a buried oxide layer (BOX) region in a semiconductor substrate, such as, a silicon wafer. In one aspect, in a method of the invention, an initial dose of oxygen ions is implanted in the substrate while maintaining the substrate temperature in a range of about 300° C. to 600° C. Subsequently, a second dose of oxygen ions is implanted in the substrate while actively cooling the substrate to maintain the substrate temperature in range of about 50° C. to 150° C. These ion implantation steps are followed by an annealing step in an oxygen containing atmosphere to form a continuous BOX region in the substrate. In one preferred embodiment, the initial ion implantation step is performed in a chamber that includes a device for heating the substrate while the second ion implantation step is performed in a separate chamber that is equipped with a device for actively cooling the substrate.

Abstract: The present invention provides a rotating shaft that can extend between two regions having different ambient pressures. The rotating shaft can include a rotatable hollow outer shell that is coupled to a proximal portion of an inner shaft with a limited number of contact points. A plurality of thermal breaks disposed between the inner shaft and the hollow outer shell impede heat transfer between these two components. A rotary seal coupled to the distal portion of the inner shaft preserves the pressure differential between the two regions. Further, a heat sink removes heat transferred to the seal to ensure that the temperature of the seal remains within a range suitable for its operation. The rotating shaft of the invention can be utilized, for example, in an ion implantation system by the coupling of the outer shell to a wafer holder to position and orient a wafer in a path of an ion beam.

Abstract: The present invention provides a method for generating silicon-on-insulator (SOI) wafers that exhibit a high electrical resistivity. In one embodiment of a method according to the teachings of the invention, a SIMOX process is sandwiched between two Full Oxygen Precipitation (FOP) cycles that sequester interstitial oxygen present in the substrate in the form of oxide precipitates, thereby enhancing the electrical resistivity of the susbtrate.

Abstract: The present invention provides a beam stop for use in an ion implantation system that includes a base formed of a thermally conductive material, and a heat transfer layer formed of a semi-elastic material that is disposed on a surface of the base. The beam stop further includes one or more tiles, each formed of a thermally conductive refractory material, that are disposed on the semi-elastic layer so as to face an ion beam in the implantation system. The heat transfer layer transfers heat generated in the tile in response to ion beam impact to the base. The base in turn can be coupled to a heat sink to remove heat from the base. The thickness and the thermal conductivity of the base, and those of the heat transfer layer and the tile are chosen so as to ensure uniform expansion of the base and the tile when the beam stop is heated by ion beam impact.

Abstract: The present invention provides a method for creation of high quality semiconductor-on-insulator structures, e.g., silicon-on-insulator structures, using implantation of sub-stoichiometric doses of oxygen at multiple energies. The method employs sequential steps of ion implantation and high temperature annealing to produce structures with a top silicon layer having a thickness ranging from 10-250 nm and a buried oxide layer having a thickness 30-300 nm. The buried oxide layer has a breakdown field greater than 5 MV/cm. Further, the density of silicon inclusions in the BOX region is less than 2×107 cm−2. The process of the invention can be used to create an entire SOI wafer, or be used to create patterned SOI, regions where SOI regions are integrated with non-SOI regions.

Abstract: Wafer-holding structures formed from thermosetting resins are disclosed for use in semiconductor processing including, for example, SIMOX wafer processing. In one embodiment a pin is disclosed that is adapted to receive a wafer edge, and is coupled with a wafer holder assembly. The pin can be filled with a conductive material to provide an electrical pathway between the wafer and the wafer holder assembly, which can be coupled to a ground. This arrangement provides a conductive path for inhibiting electrical discharges from the wafer during the ion implantation process. The pin exhibits thermal isolation characteristics and sufficient hardness so as to not effect localized thermal dissipation of the wafer, yet is sufficiently soft so as to not mark or otherwise damage the wafer.

Abstract: A wafer holder assembly includes first and second main structural members from which first and second wafer-holding arms extend. The first arm is secured to the main structural members by a graphite distal retaining member. The second arm is pivotally biased to a wafer-hold position by a graphite bias member. This arrangement provides a conductive path from the wafer to the assembly for inhibiting electrical discharges from the wafer during the ion implantation process. The assembly can further include additional graphite retaining members for maintaining the structural integrity of the assembly during the extreme conditions associated with SIMOX wafer processing without the need for potentially wafer-contaminating adhesives and conventional fasteners. The wafer-contacting pins at the distal end of the arms can be formed from silicon. The silicon pins can be coated with titanium nitride to enhance electrical contact with the wafer and to provide an abrasion resistant surface.

Abstract: The present invention provides a heating assembly that includes a thermally conductive, lamp-mounting block manufactured from aluminum or a similar material, which can be machined as a single-piece (e.g., unibody) block. The unibody block includes one or more networks of inner passageways bored or otherwise machined within the block for transporting one or more cooling fluids. The mounting block can also have a reflective coating on one or more of its surfaces that face the lamps to efficiently reflect heat and/or light generated by the lamps onto a desired surface, for example, a semiconductor wafer. Thermal isolation devices, e.g., pads, provide for both physical mounting of the heating lamps to the mounting block and also provide thermal isolation between the heating lamp and its electrical connections are also disclosed to protecting heat-sensitive elements of the heating assembly such as seals.

Abstract: The present invention provides improved ion implantation systems and methods in which a high voltage probe is utilized in an ion implantation system to directly measure energy of an ion beam incident on a substrate. More particularly, an exemplary ion implantation system can include an ion source maintained at a high electric potential that generates ions, and a plurality of extraction electrodes that can accelerate the ions to a desired energy. The system further includes an end-station, maintained at ground electric potential, in which a wafer holding for positioning a wafer in the path of an ion beam is disposed. The ion implantation system is further characterized by a high energy probe disposed between a high voltage terminus of the ion source and ground for directly measuring the energy of the ions.

Abstract: Methods of producing buried insulating layers in semiconductor substrates are disclosed whereby a dose of selected ions is implanted into a substrate to form a buried precursor layer below an upper layer of the substrate, followed by oxidation of the substrate in an atmosphere having a selected oxygen concentration to form an oxide surface layer. The oxidation is performed at a temperature and for a time duration such that the formation of the oxide layer causes the injection of a controlled number of atoms of the substrate from a region proximate to an interface between the newly formed oxide layer and the substrate into the upper regions of the substrate to reduce strain. A high temperature annealing step is then performed to produce the insulating layer within the precursor layer.

Abstract: A wafer holder assembly includes first and second main structural members from which first and second wafer-holding arms extend. The first arm is secured to the main structural members by a graphite distal retaining member. The second arm is pivotally biased to a wafer-hold position by a graphite bias member. This arrangement provides a conductive path from the wafer to the assembly for inhibiting electrical discharges from the wafer during the ion implantation process. The assembly can further include additional graphite retaining members for maintaining the structural integrity of the assembly during the extreme conditions associated with SIMOX wafer processing without the need for potentially wafer-contaminating adhesives and conventional fasteners. The wafer-contacting pins at the distal end of the arms can be formed from silicon. The silicon pins can be coated with titanium nitride to enhance electrical contact with the wafer and to provide an abrasion resistant surface.

Abstract: A wafer holder assembly includes first and second main structural members from which first and second wafer-holding arms extend. The first arm is secured to the main structural members by a graphite distal retaining member. The second arm is pivotally biased to a wafer-hold position by a graphite bias member. This arrangement provides a conductive path from the wafer to the assembly for inhibiting electrical discharges from the wafer during the ion implantation process. The assembly can further include additional graphite retaining members for maintaining the structural integrity of the assembly during the extreme conditions associated with SIMOX wafer processing without the need for potentially wafer-contaminating adhesives and conventional fasteners. The wafer-contacting pins at the distal end of the arms can be formed from silicon. The silicon pins can be coated with titanium nitride to enhance electrical contact with the wafer and to provide an abrasion resistant surface.

Abstract: A wafer holder assembly includes first and second main structural members from which first and second wafer-holding arms extend. The first arm is secured to the main structural members by a graphite distal retaining member. The second arm is pivotally biased to a wafer-hold position by a graphite bias member. This arrangement provides a conductive path from the wafer to the assembly for inhibiting electrical discharges from the wafer during the ion implantation process. The assembly can further include additional graphite retaining members for maintaining the structural integrity of the assembly during the extreme conditions associated with SIMOX wafer processing without the need for potentially wafer-contaminating adhesives and conventional fasteners. The wafer-contacting pins at the distal end of the arms can be formed from silicon. The silicon pins can be coated with titanium nitride to enhance electrical contact with the wafer and to provide an abrasion resistant surface.

Abstract: The present invention provides a method for creation of high quality semiconductor-on-insulator structures, e.g., silicon-on-insulator structures, using implantation of sub-stoichiometric doses of oxygen at multiple energies. The method employs sequential steps of ion implantation and high temperature annealing to produce structures with a top silicon layer having a thickness ranging from 10-250 nm and a buried oxide layer having a thickness 30-300 nm. The buried oxide layer has a breakdown field greater than 5 MV/cm. Further, the density of silicon inclusions in the BOX region is less than 2×107 cm−2. The process of the invention can be used to create an entire SOI wafer, or be used to create patterned SOI, regions where SOI regions are integrated with non-SOI regions.