Abstract: It is provided a driving system, a driving method, a computer system and a computer readable medium. The driving system includes: an input circuit configured to receive an input on-chip voltage and output the on-chip voltage; an adjusting circuit configured to automatically detect a present amplitude of the on-chip voltage output by the input circuit and to output a bias voltage corresponding to the present amplitude of the on-chip voltage to a gate of the driven thin film transistor, wherein a source of the thin film transistor is directly or indirectly coupled to the on-chip voltage, and the bias voltage is lower than the on-chip voltage. The protection of the transistor gate and the adjusting of a receiver threshold voltage for different I/O (input/output) voltages and levels can be completed through automatic detection of the on-chip voltage and automatic adjusting.

Abstract: A method and a control device for returning of command response information, and an electronic device are provided. The method includes: receiving response information for a command request, the response information carrying a status identification and a level identification of the command request; storing the response information in a corresponding level of a data queue in accordance with the level identification, where the data queue includes multiple levels, and each level of the data queue is used to store one or more pieces of response information; scanning all levels of the data queue, and determining, a level in which all parts of response information are collected, as a candidate level; determining a first piece of response information in accordance with a status identification of the response information stored in the candidate level; and outputting the first piece of response information.

Abstract: A voltage generation module and a power supply management chip include a reference voltage generation circuit, a comparison circuit, a switch circuit and a voltage control circuit. The reference voltage generation circuit generates a first reference voltage and a second reference voltage. The comparison circuit applies a turn-on control signal or a turn-off control signal. In the case that the switch circuit controls the input terminal to be electrically disconnected from the voltage output terminal, the voltage control circuit controls an output voltage signal from the voltage output terminal in accordance with the first reference voltage.

Abstract: This disclosure provides a voltage controlled oscillator and a control method thereof, a P2P interface circuit, an electronic device, and relates to the field of voltage controlled oscillation technology. The voltage controlled oscillator includes N stages of delay units, and the delay unit of each stage includes: a first inverter, a second inverter, a third inverter, and a fourth inverter; both the second inverter and the third inverter are electrically connected to a frequency control terminal, and whether to activate the second inverter and the third inverter is controlled by the frequency control terminal.

Abstract: The present disclosure provides a transmitter, a transceiver and a signal transmission method thereof. The transmitter comprises a signal amplification module, a balun and a feedback current generation module; the signal amplification module is configured to receive an input signal, amplify the input signal and output a differential signal to the balun; the balun is configured to receive the differential signal and convert the differential signal into a single-ended signal; and the feedback current generation module is configured to form electromagnetic coupling with the balun to generate a feedback current signal, wherein the feedback current signal is used as an input signal to a receiver.

Abstract: A method is for detecting loss-of-lock of a GNSS (Global Navigation Satellite System) signal tracking loop based on frequency compensation, comprising the following steps of: performing multi-channel frequency compensation on I-channel and Q-channel signals after down-conversion, pseudo-code stripping and integration clearing; then, performing coherent integration and non-coherent integration for a fixed time, and taking a maximum value of non-coherent integration results as a signal value; performing parabolic interpolation frequency identification, and taking an average value of the non-coherent integration results with the frequency differences of +/?50 Hz and +/?100 Hz as a noise value; and finally, calculating a ratio of the signal value to the noise value, and performing loss-of-lock detection with the ratio as a detection volume.

Abstract: The present disclosure provides an overcurrent protection circuit, an overcurrent protection method, a clock signal generation circuit and a display device. The overcurrent protection circuit includes N first overcurrent detection circuits, N second overcurrent detection circuits, a first signal generation circuit, a second signal generation circuit, a first level switching circuit, a second level switching circuit and a control circuit. The first signal generation circuit is configured to output a first control signal to the first level switching circuit upon the receipt of a first overcurrent indication signal. The second signal generation circuit is configured to output a second control signal to the second level switching circuit upon the receipt of a second overcurrent indication signal.

Abstract: Embodiments of the present application relate to the field of display driving technology, and disclose a method, an apparatus, an electronic device and a storage medium for processing pixel data. The method comprises: acquiring first image parameters of a first image unit and second image parameters of a second image unit, wherein the first image unit includes pixel data, of a first image, which is located on a first horizontal line, the second image unit includes pixel data, of a second image, which is located on the first horizontal line, and the second image is a previous frame of the first image; and updating the pixel data of the first image unit when the first image parameters do not match the second image parameters. The embodiments of the present application solve the problem of high driving power consumption in the process of outputting screens of the display panel in the prior art.

Abstract: A slew rate boosting circuit, a source driver chip and a display device are provided in the present disclosure. The slew rate boosting circuit comprises: a first latch configured to receive and store first data; a second latch configured to receive and store second data, the second data being next to the first data; a first level shifter; an amplifier; and a slew rate boosting module configured to receive a high voltage data signal as current input data, and adjust a slew rate of an output stage of the amplifier according to a value of a specified bit of the first data, a value of a specified bit of the second data and the current input data.

Abstract: The invention relates to a universal semiconductor automatic high-speed serial signal testing method, comprising: a chip to be tested sending, to an impedance matching unit, a high-speed serial signal; then by means of a phase shift unit, sequentially transforming, according to a set fixed resolution, the phase of the high-speed serial signal, the magnitude of each offset phase being determined by a phase shift control signal outputted by a control unit and the resolution of the phase shift unit; after passing through the phase shift unit, the high-speed serial signal keeps channel impedance matching by means of the impedance matching unit; the signal entering an acquisition unit, and being acquired under the action of an acquisition control signal sent by the control unit; the control unit performing signal exchange with semiconductor automatic testing equipment (ATE); and the acquisition unit transmitting the acquired signal back to the universal semiconductor ATE for algorithm operation, and then the actua

Abstract: It discloses a circuit for reducing a leakage current of a static random access memory (SRAM) memory array and a control method for the same. The circuit includes a memory array power supply voltage control module, a memory array ground terminal voltage control module and a memory array. The present invention controls the voltages on the power supply terminal and the ground terminal of the memory array through the memory array power supply voltage control module and the memory array ground terminal control module, and may reduce the actual data retention voltages of the bitcells, thereby reducing the leakage power of the SRAM in a data retention state. Meanwhile, the present invention implements the function of adjusting the data retention voltage values of the bitcells by controlling different adjustment signals to cope with different design requirements.

Abstract: A Liquid Natural Storage (LNG) tank comprising an outer mechanical support structure (20) providing a closed space housing a membrane wall of the cryogenic tank is disclosed. Spacer elements (21) is supporting a membrane wall constituted by a mixture of steel plates, steel rods, wooden beams and plywood plates.

Abstract: The present invention discloses an information management method and system for IC tests, and a storage medium. The method comprises steps of: providing test data generated by performing an IC test by an IC test platform, the IC test platform being an IC test platform having more than one stage, each stage of the IC test platform comprising a plurality of test devices: providing resource data related to the IC test, other than the test data; and analyzing the IC test according to the test data of the IC test and the resource data, to obtain result data related to the IC test. In this way, the present invention can provide technical support for utilizing the value of test data generated in IC tests.

Abstract: The present invention discloses a halo test method for an optical chip in an integrated circuit. A captured image array is processed as a circle by: dividing the array into circular patterns on the basis of the radius, reconstructing the circular patterns into a two-dimensional array according to coordinates, and then performing corresponding operations on the obtained array to obtain a desired value. By the halo test method for an optical chip in an integrated circuit provided in the present invention, without increasing any extra hardware cost and under the primary test conditions, the technical problem in the prior art that there is no well-developed method and algorithm for testing halo on a fingerprint on display (FOD) chip is solved.

Abstract: The present invention utilize a combination of wooden elements (20, 21), stainless steel membranes (22) and insulating materials in embodiments of the present invention. An object of the present invention is to be able to build the LNG tank separately from the building of the ship, and fit a complete or nearly complete LNG tank into the space of the ship hull when appropriate during the process of building the ship. Therefore, the building of the tank and the ship can be done in parallel, which by experience reduces the total time of building the ship considerably, and hence provide substantial cost savings.

Abstract: A configuration and testing method and system for an FPGA chip using a bumping process are disclosed, the method includes creating configuration files for an FPGA chip under test and storing them in a memory; reading, by a master FPGA, a configuration code stream of corresponding configuration codes from the mass memory, configuring the FPGA chip under test via an external test interface, and determining whether the configuration is successful; if the configuration is successful, converting the configuration code stream into a test signal source file that is recognizable, executable and reusable by multiple pieces of test equipment by a developed algorithm and a conversion tool; and automatically loading the test signal source file onto the FPGA chip under test in real time by advanced test equipment.

Abstract: A configuration and testing method and system for an FPGA chip using a bumping process are disclosed, the method includes creating configuration files for an FPGA chip under test and storing them in a memory; reading, by a master FPGA, a configuration code stream of corresponding configuration codes from the mass memory, configuring the FPGA chip under test via an external test interface, and determining whether the configuration is successful; if the configuration is successful, converting the configuration code stream into a test signal source file that is recognizable, executable and reusable by multiple pieces of test equipment by a developed algorithm and a conversion tool; and automatically loading the test signal source file onto the FPGA chip under test in real time by advanced test equipment.

Abstract: A test apparatus with physical separation feature is disclosed. The test apparatus includes probes (210), a peripheral circuit (220), a circuit of special function (230), wherein the peripheral circuit and the circuit of special function are separately arranged on different circuit boards (240, 250). The peripheral circuit and the circuit of special function are both electrically connected to the probes. In the test apparatus with physical separation feature, the peripheral circuit and the circuit of special function are separated in physical spaces, so that interference between the components is prevented and the testing cost is reduced.

Abstract: A compression method for compressing an original test file is disclosed. The compression method includes the following steps: defining type modules; scanning the original test file line by line in bytes and matching data of the original test file with the type modules to determine types of the data; compressing continuous data of the same type in lines and representing each compressed portion with a thumbnail. The compression method enables a browser to read test files with a fast speed by compressing test files according to the types of data.

Abstract: A test apparatus with physical separation feature is disclosed. The test apparatus includes probes (210), a peripheral circuit (220), a circuit of special function (230), wherein the peripheral circuit and the circuit of special function are separately arranged on different circuit boards (240, 250). The peripheral circuit and the circuit of special function are both electrically connected to the probes. In the test apparatus with physical separation feature, the peripheral circuit and the circuit of special function are separated in physical spaces, so that interference between the components is prevented and the testing cost is reduced.