Abstract: A chip arrangement comprising a first chip having at least one first signal interface with first coupling elements arranged along a first line in a first number density and at least one second chip with at least one second signal interface with second coupling elements arranged along a second line in a second number density, where the first and second coupling elements permit contactless signal transmission between the first and second signal interfaces, where the two chips are so arranged relative to each other that coupling elements of the first and second signal interfaces can contactlessly transmit signals with each other, where the longitudinal extent of at least one of the signal interfaces along the line associated therewith is greater than the length of the overlap of the two longitudinal extents, and where one of the signal interfaces has a greater number density of coupling elements than the other.

Abstract: The invention relates to a method for producing high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip. In order to produce these high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip, all technological method steps for producing the vertical structure of the collector, base and emitter in the active region of the npn bipolar transistors as well as for laterally structuring the collector regions, base regions and emitter regions are performed before the troughs and the gate insulating layer for the MOS transistors are produced.

Abstract: The invention relates to a method for the selective silicidation of contact areas that allow the production of highly integrated circuits, preferably in a SMOS or BiCMOS process. To this end, a metal oxide layer (14) that contains for example praseodymium oxide is deposited onto a prepared wafer (12). A silicon layer (16) and on top of said silicon layer a cover layer (18) is deposited onto the metal oxide layer (14), said cover layer being laterally structured. In a subsequent tempering step in an oxygen-free, reducing gas atmosphere the silicon layer (16) and the metal oxide layer (14) are converted to a metal silicide layer in lateral sections (20, 22) in which the cover layer (18) was previously removed.

Abstract: An electronic component is disclosed having a first layer of metallically conductive material, a second layer of semiconductor material, and a third layer between the first and second layers. The third layer comprises a dielectric and at least inhibits charge carrier transport both from the first to the second layer and also from the second to the first layer. The dielectric comprises praseodymium oxide of the form Pr2O3 in predominantly single crystal phase, and the second layer comprises silicon with a (001)- or with a (111)-crystal orientation at an interface with the third-layer.

Abstract: In accordance with the invention there is provided a semiconductor capacitor having a first semiconductor layer which forms a first capacitor electrode and which includes silicon, a second capacitor electrode and a capacitor dielectric including praseodymium oxide between the capacitor electrodes, in which provided between the capacitor dielectric including praseodymium oxide and at least the first semiconductor layer including silicon is a first thin intermediate layer representing a diffusion barrier for oxygen. In particular the thin intermediate layer can include oxynitride.

Abstract: A method of reducing a phase error caused by a plurality of error sources in a signal which is present in a digital frequency representation in the form of a sequence of a plurality of digital partial signals which are associated with a number of subcarriers (k) of a carrier. The following steps are performed for each partial signal: equalization of the partial signal (Y(i,k)), estimation of the phase error of the equalized partial signal (X(i,k)), and correction of the estimated phase error of the equalized partial signal. An embodiment of that method provides that the equalization step includes the elimination of an accumulation of a phase error of the partial signal, caused by a sampling frequency error, over the sequence of the partial signals, such that the accumulation is negligible.

Abstract: In accordance with the invention the semiconductor capacitor includes a first capacitor electrode 1, a second capacitor electrode 3 and a capacitor dielectric 5 which is arranged between the two capacitor electrodes and which includes praseodymium oxide. It is distinguished in that the second capacitor electrode 3 includes praseodymium silicide.

Abstract: A silicon-germanium hetero bipolar transistor comprising a silicon collector layer, a boron-doped silicon-germanium base layer, a silicon emitter layer and an emitter contact area. The transistor is fabricated using an epitaxy process on a surface of pure silicon. An electrically inert material is incorporated into the epitaxial layers in order to link the defects in the semiconductor structure and to reduce the outdiffusion of the dopant. Thus, a transistor for high-frequency applications can be fabricated in two ways: to increase the dopant dose of the base region or to reduce the thickness of the base layer. In particular, the concentration profile of germanium in the base layer has a general shape of a triangle or trapezoid.

Abstract: A CMOS-compatible DMOS transistor can be designed by virtue of a suitable layout configuration optionally for very high drain voltages or for power amplification at very high frequencies and which can be produced at a low level of additional cost in comparison with a conventional sub-?m production technology for CMOS circuits. A gate insulator of the transistor is of a unitary thickness under a control gate in the entire (active) region through which current flows. A zone of increased doping concentration (well region) which is near the surface and which determines the transistor threshold voltage is so arranged under the control gate that it occupies the entire area under the control gate which is on the active region and ends within a so-called drift space between the control gate and a highly doped drain region. The entire surface of the drift space is covered by a zone of the conductivity type of the drain region (VLDD), which is lowly doped in comparison with the highly doped drain region.

Abstract: A voltage-controlled oscillator device with an LC-resonant circuit, in particular for implementing integrated voltage-controlled oscillators for the lower GHz range, is disclosed. The device achieves continuous frequency tunability in a wide range in particular with a low level of phase noise and phase jitter. In the voltage-controlled oscillator, a second inductor can be periodically switched in parallel and/or in series with at least one first inductor of the LC-resonant circuit by way of a switching means actuated with the oscillator frequency. A control input of the switching means is connected to a variable dc voltage. In that respect the relationship of the duration of the conducting state and the duration of the non-conducting state of the switching means is variable within an oscillation period of the oscillator in dependence on the value of the control voltage.

Abstract: A silicon-germanium hetero bipolar transistor comprising a silicon collector layer, a boron-doped silicon-germanium base layer, a silicon emitter layer and an emitter contact area. The transistor is fabricated using an epitaxy process on a surface of pure silicon. An electrically inert material is incorporated into the epitaxial layers in order to link the defects in the semiconductor structure and to reduce the outdiffusion of the dopant. Thus, a transistor for high-frequency applications can be fabricated in two ways: to increase the dopant dose of the base region or to reduce the thickness of the base layer. In particular, an implantation or doped region having a T-shaped cross section profile is provided between the emitter layer and the emitter contact area.