Patents Assigned to III Holdings 2, LLC
  • Publication number: 20170131986
    Abstract: A method comprising of analyzing and transforming a program executable at compile-time such that a processor design objective is optimized. A method including analyzing an executable to estimate energy consumption of an application component in a processor. A method including transforming an executable to reduce energy consumption in a processor. A processor framework controlled by compiler inserted control that statically exposes parallelism in an instruction sequence. A processor framework to reduce energy consumption in an instruction memory system with compiler inserted control.
    Type: Application
    Filed: January 19, 2017
    Publication date: May 11, 2017
    Applicant: III HOLDINGS 2, LLC
    Inventors: Saurabh Chheda, Kristopher Carver, Raksit Ashok
  • Patent number: 9648102
    Abstract: A method is performed by a first server on a chip (SoC) node that is one instance of a plurality of nodes within a cluster of nodes. An operation is performed for determine if a second one of the SoC nodes in the cluster has data stored thereon corresponding to a data identifier in response to receiving a data retrieval request including the data identifier. An operation is performed for determining if a remote memory access channel exists between the SoC node and the second one of the SoC nodes. An operation is performed for access the data from the second one of the SoC nodes using the remote memory access channel after determine that the second one of the SoC nodes has the data stored thereon and that the remote memory access channel exists between the SoC node and the second one of the SoC nodes.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: May 9, 2017
    Assignee: III Holdings 2, LLC
    Inventors: Mark Bradley Davis, Prashant R. Chandra
  • Patent number: 9596468
    Abstract: A system and a method transmit data in a first codec from a first terminal to a second terminal. The first terminal establishes a connection with the second terminal and/or transmits, transfers and/or sends the data to the second terminal via the connection between the first terminal and the second terminal. The connection between the first terminal and the second terminal has a first channel and/or a second channel to transmit the data from the first terminal to the second terminal. The first terminal transmits the data in a first codec to the second terminal via the first channel and/or the second channel of the connection without receiving capabilities of and/or intentions from the second terminal. The second terminal may be incapable of receiving, of processing, of accepting and/or of displaying the data in the first codec. The capabilities of and/or the intentions from the second terminal is transmitted to the first terminal via the connection.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: March 14, 2017
    Assignee: III HOLDINGS 2, LLC
    Inventors: Ralph Neff, Ajay Rajagopal Iyer, Russell Hayashida, Osama Al-Shaykh
  • Patent number: 9588970
    Abstract: User-submitted content (e.g., stories) may be associated with descriptive metadata (intersection metadata), such as a timeframe, location, tags, and so on. Story content is presented in a virtual space, such as a forum, chatroom, or the like. Users submit collaborative content as the story is presented in the virtual space. The collaborative content is synchronized to presentation of the story. An author may replay the presentation and synchronized collaborative content and/or select portions of the collaborative content for inclusion in the story.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: March 7, 2017
    Assignee: III HOLDINGS 2, LLC
    Inventors: Peter Rinearson, James Strange, Karan Strange
  • Patent number: 9585281
    Abstract: A system and method for provisioning within a system design to allow the storage and IO resources to scale with compute resources are provided.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: February 28, 2017
    Assignee: III HOLDINGS 2, LLC
    Inventors: Arnold Thomas Schnell, Richard Owen Waldorf, David Borland
  • Patent number: 9569186
    Abstract: A method comprising of analyzing and transforming a program executable at compile-time such that a processor design objective is optimized. A method including analyzing an executable to estimate energy consumption of an application component in a processor. A method including transforming an executable to reduce energy consumption in a processor. A processor framework controlled by compiler inserted control that statically exposes parallelism in an instruction sequence. A processor framework to reduce energy consumption in an instruction memory system with compiler inserted control.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 14, 2017
    Assignee: III HOLDINGS 2, LLC
    Inventors: Saurabh Chheda, Kristopher Carver, Raksit Ashok
  • Patent number: 9531596
    Abstract: A system and method for packet switching functionality focused on network aggregation that reduces size and power requirements of typical systems are provided in which the system and method also increases bandwidth and reduces latency from typical deployed systems.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: December 27, 2016
    Assignee: III HOLDINGS 2, LLC
    Inventors: Thomas A. Volpe, Mark Davis, David Borland, Ken Goss
  • Patent number: 9509552
    Abstract: A data center security system and method are provided that leverage server systems on a chip (SOCs) and/or server fabrics. In more detail, server interconnect fabrics may be leveraged and extended to dramatically improve security within a data center.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: November 29, 2016
    Assignee: III Holdings 2, LLC
    Inventors: Mark Davis, David Borland, Jason Hobbs, Danny Marquette, Thomas A. Volpe, Ken Goss
  • Patent number: 9510176
    Abstract: In one embodiment, an apparatus can include: (i) a location receiver configured to receive position signals, and to derive location information therefrom; (ii) one or more recognition modules configured to receive usage-related inputs, and to provide a pattern therefrom; and (iii) a processor configured to receive the pattern, and to provide the location information and an emergency indication. For example, particular embodiments can advantageously provide an emergency beacon using voice or other usage-related inputs to a cellular telephone.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: November 29, 2016
    Assignee: III HOLDINGS 2, LLC
    Inventor: Michael C. Stephens, Jr.
  • Patent number: 9497583
    Abstract: A system and a method generate a recommendation on a mobile device. The system and the method may use a time, a location, a venue and/or an event to generate the recommendation. Further, the system and the method may use an event database to determine current interests of the user. Still further, the system and the method for generating a recommendation on a mobile device may use a transactional history of the user and/or behavior of other users to generate the recommendation. The system and the method may recommend, for example, digital media, news and event information, editorial content and/or physical or digital merchandise. As a result, the system and the method may generate a recommendation that corresponds to the current interests of the user.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: November 15, 2016
    Assignee: III Holdings 2, LLC
    Inventors: Andrew Jenkins, Jeff Rayfield
  • Patent number: 9479463
    Abstract: A data center security system and method are provided that leverage server systems on a chip (SOCs) and/or server fabrics. In more detail, server interconnect fabrics may be leveraged and extended to dramatically improve security within a data center.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: October 25, 2016
    Assignee: III HOLDINGS 2, LLC
    Inventors: Mark Davis, David Borland, Jason Hobbs, Danny Marquette, Thomas A. Volpe, Ken Goss
  • Patent number: 9465771
    Abstract: A server on a chip that can be a component of a node card. The server on a chip can include a node central processing unit subsystem, a peripheral subsystem, a system interconnect subsystem, and a management subsystem. The central processing unit subsystem can include a plurality of processing cores each running an independent instance of an operating system. The peripheral subsystem includes a plurality of interfaces for various configurations of storage media. The system interconnect subsystem provides for intra-node and inter-node packet connectivity. The management subsystem provides for various system and power management functionalities within the subsystems of the server on a chip.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: October 11, 2016
    Assignee: III HOLDINGS 2, LLC
    Inventors: Mark Bradley Davis, David James Borland, Arnold Thomas Schnell
  • Patent number: 9454403
    Abstract: A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: September 27, 2016
    Assignee: III HOLDINGS 2, LLC
    Inventors: Mark Bradley Davis, David James Borland
  • Patent number: 9424888
    Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: August 23, 2016
    Assignee: III HOLDINGS 2, LLC
    Inventor: Michael C. Stephens, Jr.
  • Patent number: 9405584
    Abstract: A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: August 2, 2016
    Assignee: III Holdings 2, LLC
    Inventors: Mark Davis, David James Borland
  • Patent number: 9318248
    Abstract: A spin valve element including parallelly or serially connected magnetic element groups, each magnetic element group having a plurality of magnetic elements that each include an intermediate layer of an insulating member or a nonmagnetic member sandwiched by a pair of ferromagnetic layers. The plurality of magnetic elements are further connected either in series or in parallel.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: April 19, 2016
    Assignee: III HOLDINGS 2, LLC
    Inventors: Haruo Kawakami, Yasushi Ogimoto, Eiki Adachi
  • Patent number: 9311269
    Abstract: A system and method are provided for network proxying. The network proxying may occur in a node of a fabric or across nodes in the fabric. In the network proxying, the node has a processor with a low power mode and the system remaps, by a management processor of the node, a port identifier for a processor that is in a low power mode to the management processor. The management processor then processes a plurality of packets that contain the port identifier for the processor that is in the low power mode to maintain a network presence of the node.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: April 12, 2016
    Assignee: III Holdings 2, LLC
    Inventors: Mark B Davis, David James Borland, Thomas A Volpe, Kenneth S. Goss
  • Patent number: 9304896
    Abstract: A data processing node has an inter-node messaging module including a plurality of sets of registers each defining an instance of a GET/PUT context and a plurality of data processing cores each coupled to the inter-node messaging module. Each one of the data processing cores includes a mapping function for mapping each one of a plurality of user level processes to a different one of the sets of registers and thereby to a respective GET/PUT context instance. Mapping each one of the user level processes to the different one of the sets of registers enables a particular one of the user level processes to utilize the respective GET/PUT context instance thereof for performing a GET/PUT action to a ring buffer of a different data processing node coupled to the data processing node through a fabric without involvement of an operating system of any one of the data processing cores.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: April 5, 2016
    Assignee: III Holdings 2, LLC
    Inventors: Prashant R. Chandra, Thomas A. Volpe, Mark Bradley Davis, Niall Joseph Dalton
  • Publication number: 20160085526
    Abstract: A system, for use with a compiler architecture framework, includes performing a statically speculative compilation process to extract and use speculative static information, encoding the speculative static information in an instruction set architecture of a processor, and executing a compiled computer program using the speculative static information, wherein executing supports static speculation driven mechanisms and controls.
    Type: Application
    Filed: December 9, 2015
    Publication date: March 24, 2016
    Applicant: III HOLDINGS 2, LLC
    Inventor: Csaba Andras Moritz
  • Publication number: 20160085554
    Abstract: A processing system to reduce energy consumption and improve performance in a processor, controlled by compiler inserted information ahead of a selected branch instruction, to statically expose and control how the prediction should be completed and which mechanism should be used to achieve energy and performance efficiency.
    Type: Application
    Filed: December 9, 2015
    Publication date: March 24, 2016
    Applicant: III HOLDINGS 2, LLC
    Inventors: Saurabh Chheda, Kristopher Carver, Raksit Ashok