Abstract: Circuits and associated methods for processing two floating-point numbers (A, B) to generate a sum (A+B) of the two numbers and a difference (A?B) of the two numbers include calculating (806) a sum (|A|+|B|) of the absolute values of the two floating-point numbers, using a same-sign floating-point adder (1020), to produce a first result. The method further comprises calculating (808) a difference (|A|?|B|) of the absolute values to produce a second result. The sum (A+B) and the difference (A?B) are generated (810, 812) based on the first result (|A|+|B|), the second result (|A|?|B|), and the sign of each floating-point number.

Abstract: A hardware implementation of a neural network and a method of processing data in such a hardware implementation are disclosed. Input data for a plurality of layers of the network is processed in blocks, to generate respective blocks of output data. The processing proceeds depth-wise through the plurality of layers, evaluating all layers of the plurality of layers for a given block, before proceeding to the next block.

Abstract: A compressed data structure that encodes a set of Haar coefficients for a 2×2 quad of pixels of a block of pixels is decoded. The set of Haar coefficients comprises differential coefficients and an average coefficient. A first portion of the compressed data structure encodes the differential coefficients for the 2×2 quad of pixels. A second portion of the compressed data structure encodes the average coefficient for the 2×2 quad of pixels. The first portion is used to determine signs and exponents differential coefficients which are non-zero. The second portion is used to determine a representation of the average coefficient. The result of a weighted sum of the differential coefficients and the average coefficient for the 2×2 quad of pixels is determined using: (i) the determined signs and exponents for the differential coefficients which are non-zero, (ii) the determined representation of the average coefficient, and (iii) respective weights for the differential coefficients.

Abstract: Methods and decoding units for decoding a compressed data structure to determine a decoded value. The compressed data structure encodes a set of Haar coefficients for a block of pixels, including a plurality of differential coefficients and a sum coefficient. The compressed data structure includes a set of exponent bits representing exponents of the differential coefficients, a set of sign bits representing signs for the differential coefficients, a set of sum bits representing the sum coefficient. The compressed data structure is unpacked to identify the set of exponent bits, the set of sign bits and the set of sum bits. The identified set of exponent bits is used to determine exponents for the differential coefficients. The identified set of sign bits is used to determine signs the differential coefficients. The identified set of sum bits is used to determine the sum coefficient.

Abstract: A ray tracing unit implemented in a graphics rendering system includes processing logic configured to perform ray tracing operations on rays, a dedicated ray memory coupled to the processing logic and configured to store ray data for rays to be processed by the processing logic, an interface to a memory system, and control logic configured to manage allocation of ray data to either the dedicated ray memory or the memory system. Core ray data for rays to be processed by the processing logic is stored in the dedicated ray memory, and at least some non-core ray data for the rays is stored in the memory system. This allows core ray data for many rays to be stored in the dedicated ray memory without the size of the dedicated ray memory becoming too wasteful when the ray tracing unit is not in use.

Abstract: A decoder for decoding texels of a p by q sub-block from a block of ASTC encoded texture data representing an n by m block of texels, where p?n and q?m. The decoder determines a position of a first texel of the sub-block with respect to the rows and/or columns of a weight grid comprising a first plurality of weights in a first plane; determines a position of a second texel of the sub-block with respect to the rows and/or columns of the weight grid; compares the positions of the first and second texels; extracts fewer than (p+1)(q+1) weights in response to determining that the positions of the first and second texels are between the upper-most and lower-most rows of a predetermined number of adjacent rows of the weight grid and/or the left-most and right-most columns of a predetermined number of adjacent columns of the weight grid; and decodes the texels in dependence on the extracted weights.

Abstract: An activation accelerator for use in a neural network accelerator includes a look-up table and activation pipelines. The look-up table stores values representing a non-linear activation function. Each activation pipeline comprises a range conversion unit which receives an input value and generates a converted value from the input value, an index generation unit which receives information identifying a first subset of bits of the converted value and a second subset of bits of the converted value, generates an index from the first subset of bits of the converted value, and generates an interpolation value from the second subset of bits of the converted value, a look-up table interface unit which retrieves multiple values from the look-up table based on the index, and an interpolation unit which generates an estimated result of the non-linear activation function for the input value by interpolating between the multiple values retrieved from the look-up table based on the interpolation value.

Abstract: A method of scheduling processing in a ray tracing system gathers child rays into a child task, assigns priority to the child task on the basis that one or more child rays of the child task are derived from a task to which priority has been assigned, and schedules the child task for processing in preference to one or more other tasks to be scheduled to which priority has not been assigned.

Abstract: Methods of implementing a sparse submanifold deconvolution on a graphics processing unit, the sparse submanifold deconvolution being representable as a direct convolution between an input tensor to the sparse submanifold deconvolution and each of a plurality of a sub-filters, each sub-filter of the plurality of sub-filters comprising a subset of weights of a filter of the sparse submanifold deconvolution.

Abstract: Methods and processing modules upsample a block of input pixels to determine a block of upsampled pixels. At least one of the upsampled pixels is a diagonal pixel, wherein a diagonal pixel is at a position that is not in any of the rows nor in any of the columns of input pixels in the block of input pixels. Indications of image gradients are determined for the block of input pixels. The determined indications of image gradients are used to determine one or more weighting parameters which are indicative of weights of a diagonal kernel. The upsampled pixels of the block of upsampled pixels are determined by applying kernels to the block of input pixels, wherein the diagonal pixel in the block of upsampled pixels is determined by applying the diagonal kernel to the block of input pixels in accordance with the determined one or more weighting parameters.

Abstract: A method of repacking tasks in a graphics pipeline includes, in response to a task reaching a checkpoint in a program, determining if the task is eligible for repacking. If the task is eligible for repacking, the task is de-scheduled and it is determined whether repacking conditions are satisfied. In the event that the repacking conditions are satisfied, the method looks for a pair of compatible and non-conflicting tasks at the checkpoint. If such a pair of tasks are found, one or more instances are transferred between the pair of tasks.

Abstract: A texture filtering unit has inputs arranged to receive at least two texture values each clock cycle and a plurality of filter coefficients, the plurality of filter coefficients relating to a plurality of different texture filtering methods; hardware logic arranged to convert the input texture values to fixed-point representation; a coefficient merging logic block arranged to generate a single composite filter coefficient for each input texture value from the plurality of filter coefficients; one multiplier for each input texture value, wherein each multiplier is arranged to multiply one of the input texture values by its corresponding single composite filter coefficient; an addition unit arranged to add together outputs from each of the multipliers; hardware logic arranged to convert an output from the addition unit back to floating-point format; and an output arranged to output the converted output from the addition unit.

Abstract: A method of scheduling a plurality of active GPU drivers in a GPU includes, for one or more of the plurality of active GPU drivers, allocating a portion of a scheduling interval to the active GPU driver and selecting an active GPU driver for execution according to a priority-based scheduling algorithm. In response to an active GPU driver executing within its allocated portion, the priority level of the active GPU driver is increased, in response to the active GPU driver completing its workload within its allocated portion the priority level of the active GPU driver is reset and in response to the active GPU driver executing for its whole allocated portion, the priority level of the active GPU driver is reduced. The priority levels of each active GPU driver are reset to their initial priority levels at the start of each scheduling interval.

Abstract: Segment load operations are performed by processing data through an anything-to-anything mux, and sections writing elements to respective storage locations based on corresponding indices of the elements and the storage locations. Once all of the elements are loaded into the correct storage location, each location is read again with the elements of that storage location being sent through the mux, arranged) into the correct order, and written back to the same register.

Abstract: A method of rendering an image of a 3-D scene includes rendering a noisy image and obtaining one or more guide channels. For each of a plurality of local neighborhoods, the method comprises: calculating the parameters of a model that approximates the noisy image as a function of the one or more guide channels, and applying the calculated parameters to produce a denoised image. At least one of (i) the noisy image, (ii) the one or more guide channels, and (iii) the denoised image, are stored in a quantized low-bitdepth format.

Abstract: Transforming rendered frames in a graphics processing system to obtain enhanced frames with desired characteristics of a set of target images includes selecting a plurality of shaders, each defined by a parametrized mathematical function arranged to replicate a particular visual characteristic. For each shader, parameters of the parametrized mathematical function have been derived in dependence on a set of target images so that the shader is arranged to impose its respective particular visual characteristic in dependence on an extent to which the particular visual characteristic is exhibited in the target images. The plurality of shaders are combined to form a pipeline, obtaining one or more rendered frames, applying the pipeline to at least a portion of the one or more rendered frames to obtain enhanced frames, and outputting for display the enhanced frames, wherein the enhanced frames exhibit visual characteristics of the target images.

Abstract: A circuit for mapping N coordinates to a 1D space receives N input bit-strings representing respective coordinates, which can be of different sizes; produces a grouped bit-string therefrom, in which the bits, including non-data bits, are grouped into groups of bits originating from the same bit position per group; and demultiplexes this into n=1 . . . N demultiplexed bit-strings, and sends each to a respective n-coordinate channel. The nth demultiplexed bit-string includes a respective part of the grouped bit-string that has n coordinate data bits and N-n non-data bits per group, and all other groups filled with null bits. Each but the N-coordinate channel includes bit-packing circuitry which packs down the respective demultiplexed bit-string by removing the non-data bits, and removing the same number of bits per group from the null bit.

Abstract: A method and system is provided for culling hidden objects in a tile-based graphics system before they are indicated in a display list for a tile. A rendering space is divided into a plurality of regions which may for example be a plurality of tiles or a plurality of areas into which one or more tiles are divided. Depth thresholds for the regions, which are used to identify hidden objects for culling, are updated when an object entirely covers a region and in dependence on a comparison between a depth value for the object and the depth for the region. For example, if the depth threshold is a maximum depth threshold, the depth threshold may be updated if an object entirely covers the tile and the maximum depth value of the object is less than the maximum depth threshold.

Abstract: Methods and processing modules apply adaptive sharpening, for a block of input pixels for which processing is performed, to determine a block of output pixels. A block of non-sharp processed pixels is obtained based on the block of input pixels, the block of non-sharp processed pixels being for representing a non-sharp version of the block of output pixels. A block of sharp processed pixels is obtained based on the block of input pixels, the block of sharp processed pixels being for representing a sharp version of the block of output pixels. One or more indications of contrast for the block of input pixels is determined. Each of the output pixels of the block of output pixels is determined by performing a respective weighted sum of: (i) a corresponding non-sharp processed pixel in the block of non-sharp processed pixels and (ii) a corresponding sharp processed pixel in the block of sharp processed pixels.

Abstract: A method and processor for retrieving a block of data items, each being associated with a coordinate for each of dimensions of a stored data array. A data processing unit detects that the coordinates are axis-aligned. In response to detecting that the coordinates are axis-aligned, the following are sent to a data load unit: only one coordinate for a first dimension for each line of data items aligned in the first dimension within the block, and only one coordinate for a second dimension for each line of data items aligned in the second dimension within the block, the second dimension being orthogonal to the first dimension. The data load unit: (i) processes the coordinates to generate addresses of data array elements to be fetched from the stored data array, (ii) fetches data array elements using the generated addresses, (iii) determines data item values based on the fetched data array elements, and (iv) outputs the data item values.