Patents Assigned to Imagination Technologies Limited
  • Patent number: 10841461
    Abstract: A method for enhancing an edge transition in a video signal comprising the steps of receiving a video signal including an edge transition, generating a correction signal for the edge transition, applying the correction signal to the video signal to produce a corrected signal and restricting the amplitude of the corrected signal to extend between extended maximum and minimum amplitude limits in dependence on the measured maximum and minimum amplitudes of a predefined pattern of pixels adjacent to the edge transition.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: November 17, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Stephen Morphet
  • Patent number: 10841139
    Abstract: Methods and systems for estimating a symbol timing error for an offset quadrature phase shift keying (O-QPSK) modulated signal. The method includes: receiving a plurality of complex samples representing an O-QPSK modulated signal, wherein if the O-QPSK modulated signal is sampled on time each of the plurality of samples has substantially no imaginary component; generating an early error metric and a late error metric for each sample, the early error metric based on the imaginary component for the sample and a sign of a real component of a previous sample and the late error metric based on the imaginary component for the sample and a sign of a real component of a next sample; generating a combined early error metric based on the early error metrics for the plurality of samples; generating a combined late metric based on the late error metrics for the plurality of samples; and generating an estimate of the symbol timing error based on the combined early error metric and the combined late metric.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: November 17, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Matthew Gilbert
  • Patent number: 10841431
    Abstract: An echo cancellation detector for controlling an acoustic echo canceller that is configured to cancel an echo of a far-end signal in a near-end signal in a telephony system, the echo cancellation detector comprising a comparison generator configured to compare the far-end signal with the near-end signal, a decision unit configured to make a determination about a first acoustic echo canceller based on that comparison and a controller configured to control an operation of a second acoustic echo canceller in dependence on the determination.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: November 17, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Senthil Kumar Mani, Srinivas Akella, Anupama Ghantasala
  • Patent number: 10834328
    Abstract: A user interface to a virtual camera for a 3-D rendering application provides various features. A rendering engine can continuously refine the image being displayed through the virtual camera, and the user interface can contain an element for indicating capture of the image as currently displayed, which causes saving of the currently displayed image. Autofocus (AF) and autoexposure (AE) reticles can allow selection of objects in a 3-D scene, from which an image will be rendered, for each of AE and AF. A focal distance can be determined by identifying a 3-D object visible at a pixel overlapped by the AF reticle, and a current viewpoint. The AF reticle can be hidden in response to a depth of field selector being set to infinite depth of field. The AF and AE reticles can be linked and unlinked, allowing different 3-D objects for each of AF and AE.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: November 10, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Suguru Nishioka, James McCombe, Steven Blackmon
  • Patent number: 10834403
    Abstract: A data processing system for calibrating a media codec comprising a sequence of time-stamped frames and comprising: an encoder subsystem configured to perform encoding in accordance with one or more encode parameters; a decoder subsystem; and a calibration system comprising: a data store for storing an encoded media stream; and a calibration monitor configured to, on the media codec entering a calibration mode, cause: the decoder subsystem to decode the encoded media stream so as to generate a decoded media stream; the encoder subsystem to re-encode said decoded media stream; and the re-encoded media stream to pass back into the decoder subsystem; the calibration monitor being configured to, through variation of the encode parameters of the encoder subsystem, identify maximal encode parameters corresponding to the greatest steady-state demand on the media codec that permits decoding of the sequence of time-stamped frames at a rate in accordance with their associated timestamps.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: November 10, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Venu Annamraju, Harish Rajamani, Mallikarjuna Kamarthi
  • Patent number: 10832473
    Abstract: A tessellation method uses both vertex tessellation factors and displacement factors defined for each vertex of a patch, which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves calculating a vertex tessellation factor for each corner vertex in one or more input patches. Tessellation is then performed on the plurality of input patches using the vertex tessellation factors. The tessellation operation involves adding one or more new vertices and calculating a displacement factor for each newly added vertex. A world space parameter for each vertex is subsequently determined by calculating a target world space parameter for each vertex and then modifying the target world space parameter for a vertex using the displacement factor for that vertex.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: November 10, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 10819367
    Abstract: Lossy methods and hardware for compressing data and the corresponding decompression methods and hardware are described. The lossy compression method comprises dividing a block of pixels into a number of sub-blocks and then analysing, for each sub-block, and selecting one of a candidate set of lossy compression modes. The analysis may, for example, be based on the alpha values for the pixels in the sub-block. In various examples, the candidate set of lossy compression modes comprises at least one mode that uses a fixed alpha channel value for all pixels in the sub-block and one or more modes that encode a variable alpha channel value.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: October 27, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Simon Fenney, Linling Zhang
  • Patent number: 10817973
    Abstract: A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. Computation instances are allocated to tasks using a task assembly unit which stores task entries for respective tasks. The task entries indicate which computation instances have been allocated to the respective tasks. The task entries are associated with characteristics of computation instances which can be allocated to the respective tasks. A computation instance to be executed is allocated to a task based on the characteristics of the computation instance. SIMD processing logic executes computation instances of a task outputted from the task assembly unit to thereby determine graphics data items, which can be used to render the primitives.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: October 27, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Andrea Sansottera, Xile Yang, John Howson, Jonathan Redshaw
  • Patent number: 10817367
    Abstract: Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: October 27, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Ashish Darbari, Iain Singleton
  • Patent number: 10817301
    Abstract: Methods and parallel processing units for avoiding inter-pipeline data hazards wherein inter-pipeline data hazards are identified at compile time. For each identified inter-pipeline data hazard the primary instruction and secondary instruction(s) thereof are identified as such and are linked by a counter which is used to track that inter-pipeline data hazard. Then when a primary instruction is output by the instruction decoder for execution the value of the counter associated therewith is adjusted (e.g. incremented) to indicate that there is hazard related to the primary instruction, and when primary instruction has been resolved by one of multiple parallel processing pipelines the value of the counter associated therewith is adjusted (e.g. decremented) to indicate that the hazard related to the primary instruction has been resolved.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: October 27, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Luca Iuliano, Simon Nield, Yoong-Chert Foo, Ollie Mower
  • Patent number: 10812997
    Abstract: The presence of an OFDM signal in a received input signal is detected by calculating, for each block of a plurality of blocks of samples of the received input signal, an auto-correlation value at each of a plurality of lags-of-interest; determining, for each of the plurality of lags-of-interest, a rate of growth value across a group of two or more blocks of data samples based on the auto-correlation values; normalising the determined rate of growth values using a normalisation factor to generate normalised rate of growth values; and determining whether an OFDM signal is present in the received input signal based on the normalised rate of growth values.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: October 20, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Filipe Wiener Carvalho
  • Patent number: 10810763
    Abstract: Data compression (and corresponding decompression) is used to compress blocks of data values involving processes including one or more of colour decorrelation, spatial decorrelation, entropy encoding and packing. The entropy encoding generates encoded data values which have variable sizes (in terms of the number of bits). The entropy encoding uses size indications for respective sets of data values to indicate the number of bits used for the encoded data values of the set. The size indications allow the encoded data values to be parsed quickly (e.g. in parallel).
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: October 20, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 10810708
    Abstract: A pixel filter has a filter module that performs a first recursive filter operation in a first direction through a sequence of pixels to form a first filtered pixel value for each pixel, and performs a second recursive filter operation in a second direction through the sequence of pixels to form a second filtered pixel value for each pixel, the first and second recursive filter operations forming a respective filtered pixel value for a given pixel in dependence on the pixel value at that pixel and the filtered pixel value preceding that pixel in their respective direction of operation. The filtered pixel value of the preceding pixel is scaled by a measure of similarity between data associated with that pixel and its preceding pixel. Filter logic combines the first and second filtered pixel values formed by the first and second recursive filter operations to generate a filter output for the pixel, for each pixel of the sequence.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 20, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Szabolcs Csefalvay
  • Patent number: 10812101
    Abstract: A method of data compression in which the total size of the compressed data is determined and based on that determination, the bit depth of the input data may be reduced before the data is compressed. The bit depth that is used may be determined by comparing the calculated total size to one or more pre-defined threshold values to generate a mapping parameter. The mapping parameter is then input to a remapping element that is arranged to perform the conversion of the input data and then output the converted data to a data compression element. The value of the mapping parameter may be encoded into the compressed data so that it can be extracted and used when subsequently decompressing the data.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 20, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 10802985
    Abstract: A method of GPU virtualization comprises allocating each virtual machine (or operating system running on a VM) an identifier by the hypervisor and then this identifier is used to tag every transaction deriving from a GPU workload operating within a given VM context (i.e. every GPU transaction on the system bus which interconnects the CPU, GPU and other peripherals). Additionally, dedicated portions of a memory resource (which may be GPU registers or RAM) are provided for each VM and whilst each VM can only see their allocated portion of the memory, a microprocessor within the GPU can see all of the memory. Access control is achieved using root memory management units which are configured by the hypervisor and which map guest physical addresses to actual memory addresses based on the identifier associated with the transaction.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: October 13, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Dave Roberts, Mario Sopena Novales, John W. Howson
  • Patent number: 10805196
    Abstract: A method of transmitting a stream of packets over a network, the method comprising the steps of: a transmitting device maintaining a measure of network quality; analyzing the measure of network quality so as to determine whether the bandwidth of the network is degrading, beyond a predetermined threshold, the network quality for a transmission over the network; the transmitting device determining a transmission bitrate and a proportion of redundancy in dependence on the analysis; the transmitting device packetising media data and redundancy data in dependence on the determined proportion to generate a stream of packets; and the transmitting device transmitting the generated stream at a rate commensurate with the determined transmission bitrate.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: October 13, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Senthil Kumar Mani, Bala Manikya Prasad Puram
  • Patent number: 10796052
    Abstract: Computer-implemented methods of verifying an integrated circuit hardware design to implement an integer divider wherein the integer divider is configured to receive a numerator N and a denominator D and output a quotient q and a remainder r. The method includes (a) verifying a base property is true for the integrated circuit hardware design and (b) formally verifying that one or more range reduction properties are true for the integrated circuit hardware design. The base property is configured to verify that an instantiation of the integrated circuit hardware design will generate a correct output pair q,r in response to any input pair N,D in a subset of non-negative input pairs.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: October 6, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Emiliano Morini, Sam Elliott
  • Patent number: 10789758
    Abstract: Ray tracing, and more generally, graphics operations taking place in a 3-D scene, involve a plurality of constituent graphics operations. Responsibility for executing these operations can be distributed among different sets of computation units. The sets of computation units each can execute a set of instructions on a parallelized set of input data elements and produce results. These results can be that the data elements can be categorized into different subsets, where each subset requires different processing as a next step. The data elements of these different subsets can be coalesced so that they are contiguous in a results set. The results set can be used to schedule additional computation, and if there are empty locations of a scheduling vector (after accounting for the members of a given subset), then those empty locations can be filled with other data elements that require the same further processing as that subset.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 29, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Luke T. Peterson, James A. McCombe, Ryan R. Salsbury, Stephen Purcell
  • Patent number: 10782730
    Abstract: A first device operates synchronously with a second device, and includes a hardware clock having an adjustable clock frequency and a software clock configured to derive time in dependence on the hardware clock. A controller determines a synchronisation error between the software clock and a clock of the second device, and adjusts the clock frequency of the hardware clock in dependence on the synchronisation error so as to synchronise the hardware clock to a hardware clock of the second device.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: September 22, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Martin Woodhead, Arnold Mark Bilstad
  • Patent number: 10783605
    Abstract: Aspects include a multistage collector to receive outputs from plural processing elements. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more ALUs that may perform SIMD operations on a data vector and produce outputs according to the instruction stream being used to configure the ALU(s). The multistage collector includes substituent components each with at least one input queue, a memory, a packing unit, and an output queue; these components can be sized to process groups of input elements of a given size, and can have multiple input queues and a single output queue. Some components couple to receive outputs from the ALUs and others receive outputs from other components. Ultimately, the multistage collector can output groupings of input elements. Each grouping of elements (e.g., at input queues, or stored in the memories of component) can be formed based on matching of index elements.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: September 22, 2020
    Assignee: Imagination Technologies Limited
    Inventors: James Alexander McCombe, Steven John Clohset, Jason Rupert Redgrave, Luke Tilman Peterson