Abstract: A datapath pipeline which uses replicated logic blocks to increase the throughput of the pipeline is described. In an embodiment, the pipeline, or a part thereof, comprises a number of parallel logic paths each comprising the same logic. Input register stages at the start of each logic path are enabled in turn on successive clock cycles such that data is read into each logic path in turn and the logic in the different paths operates out of phase. The output of the logic paths is read into one or more output register stages and the logic paths are combined using a multiplexer which selects an output from one of the logic paths on any clock cycle. Various optimization techniques are described and in various examples, register retiming may also be used. In various examples, the datapath pipeline is within a processor.

Abstract: A method of compressing a set of image value data items each representing a position in image-value space so as to define an occupied region thereof. A series of compression transforms is applied to subsets of the image data items to generate a transformed set of image data items occupying a compacted region of value space. A set of one or more reference data items is identified that quantizes the compacted region in value space. For each image data item in the set of image data items, a sequence of decompression transforms is identified that generates an approximation of that image data item when applied to a selected one of the reference data items. Each image data item is encoded as a representation of the identified sequence of decompression transforms for that image data item. The data items and the decompression transforms are stored as compressed image data.

Abstract: Described herein are hardware monitors arranged to detect illegal firmware instructions in a firmware binary image using a hardware design and one or more formal assertions. The hardware monitors include monitor and detection logic configured to detect when an instantiation of the hardware design has started and/or stopped execution of the firmware and to detect when the instantiation of the hardware design has decoded an illegal firmware instruction. The hardware monitors also include assertion evaluation logic configured to determine whether the firmware binary image comprises an illegal firmware instruction by evaluating one or more assertions that assert that if a stop of firmware execution has been detected, that a decode of an illegal firmware instruction has (or has not) been detected.

Abstract: A method and graphics processing unit (GPU) are provided for applying texture processing to a block of fragments, each of the fragments being associated with a texture coordinate for each of a plurality of dimensions of a texture. A fragment processing unit of the GPU detects that the texture coordinates for the fragments of the block are axis-aligned, and in response to detecting that the texture coordinates for the fragments of the block are axis-aligned, sends a reduced set of texture coordinates to a texture processing unit of the GPU. The texture processing unit: (i) processes the reduced set of texture coordinates to generate texel addresses of texels to be fetched, (ii) fetches texels using the generated texel addresses, (iii) determines a processed value for each of the fragments of the block based on the fetched texels, and (iv) outputs the processed values.

Abstract: A method and processor for retrieving a block of data items in a processor, each of the data items being associated with a coordinate for each dimension of a stored data array. A data processing unit detects that the coordinates associated with the data items are axis-aligned. A data load unit: (i) determines integer coordinates for each of a set of the coordinates, (ii) performs a uniquification process on the determined integer coordinates to remove duplicated integer coordinates and to determine a subset of the determined integer coordinates, (iii) uses the subset of the determined integer coordinates to generate addresses of data array elements to be fetched from the stored data array, (iv) fetches data array elements from the stored data array using the generated addresses, (v) for each of the data items of the block, determines a data item value using a sub-group of the fetched data array elements, and (vi) outputs the data item values.

Abstract: A method of mapping a neural network to hardware uses a binary tree to assess how to split a layer of the neural network into a plurality of hardware passes by determining a starting value of a current depth within the binary tree and arranging the set of coefficients into groups, each corresponding to a node at the current depth. A compressed size of at least one group of coefficients at the current depth is calculated and it is determined whether termination criteria are satisfied. In response to determining that the termination criteria are not satisfied, the current depth is updated and the calculating and determining steps are repeated. In response to determining that termination criteria are satisfied, data is output which defines each of the plurality of hardware passes, wherein the data is dependent upon the current depth.

Abstract: A method of performing lossy compression on a block of image data in accordance with a multi-level difference table determines an origin value for the block of image data, and determines a level within the multi-level difference table for the block of image data, by determining a maximum difference between the determined origin value and any one of image element values in the block of image data and selecting from the multi-level difference table the level whose largest entry most closely represents the determined maximum difference. For each image element value in the block, one of the entries at the determined level within the multi-level difference table is selected, and a compressed block of data for the block of image data is formed, the compressed block of data including (i) data representing the determined origin value, (ii) an indication of the determined level, and (iii) for each image element value in the block of image data, an indication of the selected entry for that image element value.

Abstract: A computer-implemented method for performing a vector bitwise rotation, wherein a processing system comprises a byte-wise anything-to-anything mux and one or more bitwise right shifters, wherein the byte-wise anything-to-anything mux includes a plurality of byte-sized inputs and a plurality of byte-sized outputs, each input being associated with a respective input position and each output being associated with a respective output position. A combination of a byte-wise anything-to-anything mux and one or more bitwise shifts is used to perform vector bitwise rotations, with even and odd elements of the vector operated on separately.

Abstract: Methods and processing modules apply adaptive sharpening, for a block of input pixels for which upsampling is performed, to determine a block of output pixels. A block of upsampled pixels is obtained based on the block of input pixels. One or more range kernels is determined based on a plurality of upsampled pixels of the block of upsampled pixels. Each of the one or more range kernels is combined with a sharpening kernel to determine one or more bilateral sharpening kernels. The one or more bilateral sharpening kernels are used to determine the output pixels of the block of output pixels.

Abstract: Methods for implementing or synthesizing functions in hardware and fixed-function hardware include generating a look-up table, LUT, representing the function and then applying a transform to the LUT to transform the LUT into a plurality of derived LUTs. The transform may be applied recursively. A hardware design implementing each of the derived LUTs in fixed-function hardware logic, along with a logic unit that performs the inverse transform, is then created.

Abstract: A data compression method comprises encoding groups of data items by generating, for each group, header data comprising h-bits and a plurality of body portions each comprising b-bits and each body portion corresponding to a data item in the group. The value of h may be fixed for all groups and the value of b is fixed within a group, wherein the header data for a group comprises an indication of b for the body portions of that group. In various examples, b=0 and so there are no body portions. In examples where b is not equal to zero, a body data field is generated for each group by interleaving bits from the body portions corresponding to data items in the group. The resultant encoded data block, comprising the header data and, where present, the body data field can be written to memory.

Abstract: A particular comparison operation in ray tracing is performed using floating point values received in scalar format. The received values are promoted to vector format, wherein the received floating point values are used as a first component of vector floating point values. A second component of the vector floating point values is set to a non-zero, finite value. The comparison operation uses the vector floating point values to determine a vector result having first and second components. A scalar result of the particular comparison operation is determined, the magnitude of the scalar result being given by the magnitude of the first component. If the first component is non-zero, the sign of the scalar result equals the sign of the first component. If the first component is zero and the second component is non-zero, the sign of the scalar result equals the sign of the second component of the vector result.

Abstract: Circuits and associated methods for processing two floating-point numbers (A, B) to generate a sum (A+B) of the two numbers and a difference (A?B) of the two numbers include calculating (806) a sum (|A|+|B|) of the absolute values of the two floating-point numbers, using a same-sign floating-point adder (1020), to produce a first result. The method further comprises calculating (808) a difference (|A|?|B|) of the absolute values to produce a second result. The sum (A+B) and the difference (A?B) are generated (810, 812) based on the first result (|A|+|B|), the second result (|A|?|B|), and the sign of each floating-point number.

Abstract: A hardware implementation of a neural network and a method of processing data in such a hardware implementation are disclosed. Input data for a plurality of layers of the network is processed in blocks, to generate respective blocks of output data. The processing proceeds depth-wise through the plurality of layers, evaluating all layers of the plurality of layers for a given block, before proceeding to the next block.

Abstract: A compressed data structure that encodes a set of Haar coefficients for a 2×2 quad of pixels of a block of pixels is decoded. The set of Haar coefficients comprises differential coefficients and an average coefficient. A first portion of the compressed data structure encodes the differential coefficients for the 2×2 quad of pixels. A second portion of the compressed data structure encodes the average coefficient for the 2×2 quad of pixels. The first portion is used to determine signs and exponents differential coefficients which are non-zero. The second portion is used to determine a representation of the average coefficient. The result of a weighted sum of the differential coefficients and the average coefficient for the 2×2 quad of pixels is determined using: (i) the determined signs and exponents for the differential coefficients which are non-zero, (ii) the determined representation of the average coefficient, and (iii) respective weights for the differential coefficients.

Abstract: Methods and decoding units for decoding a compressed data structure to determine a decoded value. The compressed data structure encodes a set of Haar coefficients for a block of pixels, including a plurality of differential coefficients and a sum coefficient. The compressed data structure includes a set of exponent bits representing exponents of the differential coefficients, a set of sign bits representing signs for the differential coefficients, a set of sum bits representing the sum coefficient. The compressed data structure is unpacked to identify the set of exponent bits, the set of sign bits and the set of sum bits. The identified set of exponent bits is used to determine exponents for the differential coefficients. The identified set of sign bits is used to determine signs the differential coefficients. The identified set of sum bits is used to determine the sum coefficient.

Abstract: A ray tracing unit implemented in a graphics rendering system includes processing logic configured to perform ray tracing operations on rays, a dedicated ray memory coupled to the processing logic and configured to store ray data for rays to be processed by the processing logic, an interface to a memory system, and control logic configured to manage allocation of ray data to either the dedicated ray memory or the memory system. Core ray data for rays to be processed by the processing logic is stored in the dedicated ray memory, and at least some non-core ray data for the rays is stored in the memory system. This allows core ray data for many rays to be stored in the dedicated ray memory without the size of the dedicated ray memory becoming too wasteful when the ray tracing unit is not in use.

Abstract: A decoder for decoding texels of a p by q sub-block from a block of ASTC encoded texture data representing an n by m block of texels, where p?n and q?m. The decoder determines a position of a first texel of the sub-block with respect to the rows and/or columns of a weight grid comprising a first plurality of weights in a first plane; determines a position of a second texel of the sub-block with respect to the rows and/or columns of the weight grid; compares the positions of the first and second texels; extracts fewer than (p+1)(q+1) weights in response to determining that the positions of the first and second texels are between the upper-most and lower-most rows of a predetermined number of adjacent rows of the weight grid and/or the left-most and right-most columns of a predetermined number of adjacent columns of the weight grid; and decodes the texels in dependence on the extracted weights.

Abstract: An activation accelerator for use in a neural network accelerator includes a look-up table and activation pipelines. The look-up table stores values representing a non-linear activation function. Each activation pipeline comprises a range conversion unit which receives an input value and generates a converted value from the input value, an index generation unit which receives information identifying a first subset of bits of the converted value and a second subset of bits of the converted value, generates an index from the first subset of bits of the converted value, and generates an interpolation value from the second subset of bits of the converted value, a look-up table interface unit which retrieves multiple values from the look-up table based on the index, and an interpolation unit which generates an estimated result of the non-linear activation function for the input value by interpolating between the multiple values retrieved from the look-up table based on the interpolation value.

Abstract: A method of scheduling processing in a ray tracing system gathers child rays into a child task, assigns priority to the child task on the basis that one or more child rays of the child task are derived from a task to which priority has been assigned, and schedules the child task for processing in preference to one or more other tasks to be scheduled to which priority has not been assigned.