Patents Assigned to Imagination Technologies Limited
  • Patent number: 12223586
    Abstract: Aspects relate to tracing rays in 3-D scenes that comprise objects that are defined by or with implicit geometry. In an example, a trapping element defines a portion of 3-D space in which implicit geometry exist. When a ray is found to intersect a trapping element, a trapping element procedure is executed. The trapping element procedure may comprise marching a ray through a 3-D volume and evaluating a function that defines the implicit geometry for each current 3-D position of the ray. An intersection detected with the implicit geometry may be found concurrently with intersections for the same ray with explicitly-defined geometry, and data describing these intersections may be stored with the ray and resolved.
    Type: Grant
    Filed: December 30, 2023
    Date of Patent: February 11, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Cuneyt Ozdas, Luke Tilman Peterson, Steven Blackmon, Steven John Clohset
  • Patent number: 12223583
    Abstract: During tracing of a primary ray in a 3-D space (e.g., a 3-D scene in graphics rendering), a ray is found to intersect a primitive (e.g., a triangle) located in the 3-D space. Secondary ray(s) may be generated for a variety of purposes. For example, occlusion rays may be generated to test occlusion of a point of intersection between the primary ray and primitive is illuminated by any of the light(s). An origin for each secondary ray can be modified from the intersection point based on characteristics of the primitive intersected. For example, an offset from the intersection point can be calculated using barycentric coordinates of the intersection point and interpolation of one or more parameters associated with vertices defining the primitive. These parameters may include a size of the primitive and differences between a geometric normal for the primitive and a respective additional vector supplied with each vertex.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: February 11, 2025
    Assignee: Imagination Technologies Limited
    Inventor: Aaron Dwyer
  • Patent number: 12223351
    Abstract: A method of scheduling tasks in a processor comprises receiving a plurality of tasks that are ready to be executed, i.e. all their dependencies have been met and all the resources required to execute the task are available, and adding the received tasks to a task queue (or “task pool”). The number of tasks that are executing is monitored and in response to determining that an additional task can be executed by the processor, a task is selected from the task pool based at least in part on a comparison of indications of resources used by tasks being executed and indications of resources used by individual tasks in the task pool and the selected task is then sent for execution.
    Type: Grant
    Filed: September 11, 2023
    Date of Patent: February 11, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Isuru Herath, Richard Broadhurst
  • Patent number: 12217352
    Abstract: Graphics processing systems and methods provide soft shadowing effects into rendered images. This is achieved in a simple manner which can be implemented in real-time without incurring high processing costs so it is suitable for implementation in low-cost devices. Rays are cast from positions on visible surfaces corresponding to pixel positions towards the center of a light, and occlusions of the rays are determined. The results of these determinations are used to apply soft shadows to the rendered pixel values.
    Type: Grant
    Filed: June 19, 2023
    Date of Patent: February 4, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Justin P. DeCell, Luke T. Peterson
  • Patent number: 12217358
    Abstract: 3-D rendering systems include a rasterization section that can fetch untransformed geometry, transform geometry and cache data for transformed geometry in a memory. As an example, the rasterization section can transform the geometry into screen space. The geometry can include one or more of static geometry and dynamic geometry. The rasterization section can query the cache for presence of data pertaining to a specific element or elements of geometry, and use that data from the cache, if present, and otherwise perform the transformation again, for actions such as hidden surface removal. The rasterization section can receive, from a geometry processing section, tiled geometry lists and perform the hidden surface removal for pixels within respective tiles to which those lists pertain.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: February 4, 2025
    Assignee: Imagination Technologies Limited
    Inventor: John W. Howson
  • Patent number: 12217020
    Abstract: In an aspect, a processor includes circuitry for iterative refinement approaches, e.g., Newton-Raphson, to evaluating functions, such as square root, reciprocal, and for division. The circuitry includes circuitry for producing an initial approximation; which can include a LookUp Table (LUT). LUT may produce an output that (with implementation-dependent processing) forms an initial approximation of a value, with a number of bits of precision. A limited-precision multiplier multiplies that initial approximation with another value; an output of the limited precision multiplier goes to a full precision multiplier circuit that performs remaining multiplications required for iteration(s) in the particular refinement process being implemented. For example, in division, the output being calculated is for a reciprocal of the divisor.
    Type: Grant
    Filed: December 26, 2023
    Date of Patent: February 4, 2025
    Assignee: Imagination Technologies Limited
    Inventor: Leonard Rarick
  • Patent number: 12217161
    Abstract: A method of configuring a hardware implementation of a Convolutional Neural Network (CNN), the method comprising: determining, for each of a plurality of layers of the CNN, a first number format for representing weight values in the layer based upon a distribution of weight values for the layer, the first number format comprising a first integer of a first predetermined bit-length and a first exponent value that is fixed for the layer; determining, for each of a plurality of layers of the CNN, a second number format for representing data values in the layer based upon a distribution of expected data values for the layer, the second number format comprising a second integer of a second predetermined bit-length and a second exponent value that is fixed for the layer; and storing the determined number formats for use in configuring the hardware implementation of a CNN.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: February 4, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Clifford Gibson, James Imber
  • Patent number: 12217328
    Abstract: Aspects include a multistage collector to receive outputs from plural processing elements. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more ALUs that may perform SIMD operations on a data vector and produce outputs according to the instruction stream being used to configure the ALU(s). The multistage collector includes substituent components each with at least one input queue, a memory, a packing unit, and an output queue; these components can be sized to process groups of input elements of a given size, and can have multiple input queues and a single output queue. Some components couple to receive outputs from the ALUs and others receive outputs from other components. Ultimately, the multistage collector can output groupings of input elements. Each grouping of elements (e.g., at input queues, or stored in the memories of component) can be formed based on matching of index elements.
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: February 4, 2025
    Assignee: Imagination Technologies Limited
    Inventors: James Alexander McCombe, Steven John Clohset, Jason Rupert Redgrave, Luke Tilman Peterson
  • Patent number: 12211135
    Abstract: A method and an intersection testing module in a ray tracing system for determining whether a ray intersects a three-dimensional axis-aligned box. It is determined whether a first condition is satisfied, wherein the first condition is, or is equivalent to, ? "\[LeftBracketingBar]" C x - C z ? D x D z ? "\[RightBracketingBar]" ? H z ? D x D z + H x . It is determined whether a second condition is satisfied, wherein the second condition is, or is equivalent to, ? "\[LeftBracketingBar]" C y - C z ? D y D z ? "\[RightBracketingBar]" ? H z ? D y D z + H y .
    Type: Grant
    Filed: August 29, 2023
    Date of Patent: January 28, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Simon Fenney, Rostam King, Peter Smith-Lacey, Gregory Clark
  • Patent number: 12211118
    Abstract: A graphics processing system for generating a rendering output includes geometry processing logic having first transformation logic configured to transform a plurality of untransformed primitives into a plurality of transformed primitives, the first transformation logic configured to implement one or more expansion transformation stages which generate one or more sub-primitives; a primitive block generator configured to divide the plurality of transformed primitives into a plurality of groups; and generate an untransformed primitive block for each group comprising (i) information identifying the untransformed primitives related to the transformed primitives in the group; and (ii) an expansion transformation stage mask for at least one or more expansion transformation stages that indicates the sub-primitives generated for the untransformed primitives in that untransformed primitive block used in generating the rendering output.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: January 28, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Robert Brigg, John Howson, Xile Yang
  • Patent number: 12211136
    Abstract: Systems and methods of geometry processing, for rasterization and ray tracing processes provide for pre-processing of source geometry, such as by tessellating or other procedural modification of source geometry, to produce final geometry on which a rendering will be based. An acceleration structure (or portion thereof) for use during ray tracing is defined based on the final geometry. Only coarse-grained elements of the acceleration structure may be produced or retained, and a fine-grained structure within a particular coarse-grained element may be Produced in response to a collection of rays being ready for traversal within the coarse grained element. Final geometry can be recreated in response to demand from a rasterization engine, and from ray intersection units that require such geometry for intersection testing with primitives. Geometry at different resolutions can be generated to respond to demands from different rendering components.
    Type: Grant
    Filed: January 26, 2023
    Date of Patent: January 28, 2025
    Assignee: Imagination Technologies Limited
    Inventors: John W. Howson, Luke T. Peterson
  • Patent number: 12204448
    Abstract: A plurality of work items are processed through a processing pipeline comprising a plurality of stages in processing logic. The processing of a work item includes: (i) reading data in accordance with a memory address associated with the work item, (ii) updating the read data, and (iii) writing the updated data in accordance with the memory address associated with the work item. The method includes processing a first work item and a second work item through the processing pipeline, wherein the processing of the first work item through the pipeline is initiated earlier than the processing of the second work item, and where it is determined that the first and second work items are associated with the same memory address, first updated data of the first work item is written to a register in the processing logic, and the processing of the second work item comprises reading the first updated data from the register instead of reading data from the memory.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: January 21, 2025
    Assignee: Imagination Technologies Limited
    Inventor: Tijmen Spreij
  • Patent number: 12205248
    Abstract: An image processing method and an image processing unit for performing image processing determines a set of one or more filtered pixel values, wherein the one or more filtered pixel values represent a result of processing image data using a set of one or more filtering functions. A total covariance of the set of one or more filtering functions is identified. A refinement filtering function is applied to the set of one or more filtered pixel values to determine a set of one or more refined pixel values, wherein the refinement filtering function has a covariance that is determined based on the total covariance of the set of one or more filtering functions.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: January 21, 2025
    Assignee: Imagination Technologies Limited
    Inventor: Rostam King
  • Patent number: 12205256
    Abstract: A reduced noise image can be formed from a set of images. One of the images of the set can be selected to be a reference image and other images of the set are transformed such that they are better aligned with the reference image. A measure of the alignment of each image with the reference image is determined. At least some of the transformed images can then be combined using weights which depend on the alignment of the transformed image with the reference image to thereby form the reduced noise image. By weighting the images according to their alignment with the reference image the effects of misalignment between the images in the combined image are reduced. Furthermore, motion correction may be applied to the reduced noise image.
    Type: Grant
    Filed: September 11, 2023
    Date of Patent: January 21, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Marc Vivet, Paul Brasnett
  • Patent number: 12204872
    Abstract: Apparatus includes hardware logic arranged to normalise an n-bit input number. The hardware logic comprises at least a first hardware logic stage, an intermediate hardware logic stage and a final hardware logic stage. Each stage comprises a left shifting logic element, the first and intermediate stages each also comprise a plurality of OR-reduction logic elements and the intermediate and final stages each also comprise one or more multiplexers. The OR-reduction logic elements operate on different subsets of bits from the number input to the particular stage. In the intermediate and final hardware logic stages, a first of the multiplexers selects an OR-reduction result received from a previous hardware logic stage and the left shifting logic element is arranged to perform left shifting on the updated binary number received from an immediately previous hardware logic stage dependent upon the selected OR-reduction result.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: January 21, 2025
    Assignee: Imagination Technologies Limited
    Inventor: Casper Van Benthem
  • Patent number: 12198307
    Abstract: A method of rendering an image of a 3-D scene includes rendering a noisy image at a first resolution; obtaining one or more guide channels at the first resolution, and obtaining one or more corresponding guide channels at a second resolution. The second resolution may be the same resolution as, or a higher resolution than, the first resolution. For each of a plurality of local neighbourhoods, the method comprises: calculating the parameters of a model that approximates the noisy image as a function of the one or more guide channels (at the first resolution), and applying the calculated parameters to the one or more guide channels at the second resolution, to produce a denoised image at the second resolution.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: January 14, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Szabolcs Cséfalvay, James Imber, David Walton, Insu Yu
  • Patent number: 12197835
    Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kth difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.
    Type: Grant
    Filed: September 18, 2023
    Date of Patent: January 14, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Sam Elliott, Robert McKemey, Max Freiburghaus
  • Patent number: 12198230
    Abstract: A texture filtering unit applies anisotropic filtering using a filter kernel which can be adapted to apply different amounts of anisotropy up to a maximum amount of anisotropy. If it is determined that a received input amount of anisotropy is not above the maximum amount of anisotropy, the filter kernel applies the input amount of anisotropy, and texels of a texture are sampled using the filter kernel to determine a filtered texture value.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: January 14, 2025
    Assignee: Imagination Technologies Limited
    Inventor: Rostam King
  • Patent number: 12198034
    Abstract: A data processing system and method are disclosed, for implementing a windowed operation in at least three traversed dimensions. The data processing system maps the windowed operation in at least three traversed dimensions to a plurality of constituent windowed operations in two traversed dimensions. This plurality of 2-D windowed operations is implemented as such in at least one hardware accelerator. The data processing system assembles the results of the constituent 2-D windowed operations to produce the result of the windowed operation in at least three traversed dimensions.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: January 14, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Ivaxi Sheth, Aria Ahmadi, James Imber, Cagatay Dikici
  • Patent number: 12198254
    Abstract: Aspects comprise systems implementing 3-D graphics processing functionality in a multiprocessing system. Control flow structures are used in scheduling instances of computation in the multiprocessing system, where different points in the control flow structure serve as points where deferral of some instances of computation can be performed in favor of scheduling other instances of computation. In some examples, the control flow structure identifies particular tasks, such as intersection testing of a particular portion of an acceleration structure, and a particular element of shading code. In some examples, the aspects are used in 3-D graphics processing systems that can perform ray tracing based rendering.
    Type: Grant
    Filed: October 30, 2023
    Date of Patent: January 14, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Luke T. Peterson, James Alexander McCombe, Ryan R. Salsbury, Steven J. Clohset