Abstract: A method of activating scheduling instructions within a parallel processing unit includes checking if an ALU targeted by a decoded instruction is full by checking a value of an ALU work fullness counter stored in the instruction controller and associated with the targeted ALU. If the targeted ALU is not full, the decoded instruction is sent to the targeted ALU for execution and the ALU work fullness counter associated with the targeted ALU is updated. If, however, the targeted ALU is full, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state. When an ALU changes from being full to not being full, the scheduler is triggered to re-activate an oldest scheduled task waiting for the ALU by removing the oldest scheduled task from the non-active state.

Abstract: Ray tracing systems and computer-implemented methods for generating a hierarchical acceleration structure for intersection testing in a ray tracing system. Nodes of the hierarchical acceleration structure are determined, wherein each of the nodes represents a region in a scene, and wherein the nodes are linked to form the hierarchical acceleration structure. Data is stored representing the hierarchical acceleration structure including data defining the regions represented by a plurality of the nodes of the hierarchical acceleration structure. At least one node is an implicitly represented node, wherein data defining a region represented by an implicitly represented node is not explicitly included as part of the stored data but can be inferred from the stored data.

Abstract: Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.

Abstract: Methods and systems of generating gradients of a loss metric for a neural network (NN) with respect to weights of a convolution layer of the NN, the convolution layer of the NN configured to receive an input tensor of input values and a weight tensor of weights, and generate an output tensor of output values.

Abstract: A block of sub-primitive presence indications for use in intersection testing in a rendering system is compressed into a block of compressed data. Spatial decorrelation is performed to determine spatially decorrelated presence indications by (i) determining a predicted value for the presence indication based on one or more other presence indications in the line, and (ii) replacing the presence indication with a value of a difference between the presence indication and the determined predicted value for the presence indication. For each line of presence indications in a second dimension within the block, for one or more of the presence indications in the line: (i) a predicted value for the presence indication is determined based on one or more other presence indications in the line, and (ii) the presence indication is replaced with a value of a difference between the presence indication and the determined predicted value for the presence indication.

Abstract: A method of processing instructions at a processing unit having a parallel processing engine. During a mission cycle, a first set of mission operand values is processed in accordance with a mission instruction at a first processing instance to generate a first mission output. In parallel, a second set of mission operand values is processed in accordance with the mission instruction at a second processing instance to generate a second mission output. During a test cycle, a first set of test operand values is processed in accordance with a test instruction at the first processing instance to generate a first test output, and in parallel, a second set of test operand values is processed in accordance with the test instruction at the second processing instance to generate a second test output, where the first set of test operand values is the same as the second set of test operand values.

Abstract: Methods and storage unit allocators for allocating one or more portions of a storage unit to a plurality of tasks for storing at least two types of data. The method includes receiving a request for one or more portions of the storage unit to store a particular type of data of the at least two types of data for a task of the plurality of tasks; associating the request with one of a plurality of virtual partitionings of the storage unit based on one or more characteristics of the request, each virtual partitioning allotting none, one, or more than one portion of the storage unit to each of the at least two types of data; and allocating the requested one or more portions of the storage unit to the task from the none, one, or more than one portion of the storage unit allotted to the particular type of data in the virtual partitioning associated with the request.

Abstract: Coarse depth testing is performed in a graphics processing system having a rendering space divided into a plurality of tiles. A depth range for a tile identifies a depth range based on primitives previously processed. A determination is made based on the depth range as to whether all or a portion of a primitive is hidden in the tile. If at least a portion is not hidden in the tile, a determination is made as to whether the primitive or a primitive fragment thereof has better depth than the primitives previously processed. If so, the primitive or primitive fragment is identified as not requiring a read of a depth buffer to perform full resolution depth testing, such that a determination that at least a portion of the primitive is hidden in the tile causes full resolution depth testing not to be performed on at least that portion of the primitive.

Abstract: A method of controlling a memory device in which the memory device has a normal mode in which the memory device is operable, and a power save mode in which the memory device is inoperable and consumes lower power than the normal mode. The method includes determining a metric based on the time spent by the memory device in at least one previous inactive period. The method further includes comparing the metric with a threshold. Further the method includes in response to determining that the metric is lower than the threshold causing the memory device to remain in the normal mode throughout a subsequent inactive period.

Abstract: An aspect includes an apparatus for evaluating a mathematical function at an input value. The apparatus includes a selector for selecting a mathematical function, an input for a value at which to evaluate the function, an identifier for identifying an interval containing the input value. The interval is described by at least one polynomial function. At least one control point representing the polynomial function is retrieved from at least one look up table, and the polynomial function can be derived from the control points. The function is evaluated at the input value and an output of the evaluation is used as a value of the function at that input value.

Abstract: A computer implemented method converts ray data for a ray into a ray representative, wherein the ray representative is a compressed representation of the ray data, and wherein the ray data comprises three direction components and three position components for the ray. The method comprises identifying which of the three direction components of the ray data has the greatest magnitude, and defining the axis of the identified direction component as the major axis of the ray. The method further comprises determining a translated position on the ray at which the position component along the major axis is zero, and rescaling the three direction components of the ray so that the magnitude of the direction component along the major axis is one. The ray representative comprises: (i) the two position components of the translated position along the axes which are not the major axis, and (ii) the two rescaled direction components along the axes which are not the major axis.

Abstract: A system and method for performing intersection testing of rays in a ray tracing system. The ray tracing system uses a hierarchical acceleration structure comprising a plurality of nodes, each identifying one or more elements able to be intersected by a ray. The system makes use of a serial-mode ray intersection process, in which, when a ray intersects a bounding volume, a limited number of new ray requests are generated.

Abstract: Input pixel data having first, second and third channel data for each pixel of a block of data is received in raster scan order and is compressed in raster scan order using a block-based encoding scheme. The compressed pixel data is then output in raster scan order.

Abstract: A method and hardware for performing hardware efficient unbiased rounding of a number includes receiving the number in a binary format having a first portion and a second portion. The first portion comprises bits of the number above a rounding point and the second portion comprises bits of the number after the rounding point. The method includes adding a first amount to the number to obtain a first value. Further the method comprises determining if the bit above the rounding point for a controlling value is ‘0’ bit or a ‘1’ bit. The controlling value is either the received number in the binary format or the first value. The method further includes adding a second amount to ‘b+1’ LSBs of the first value to obtain a second value if the bit above the rounding point for the controlling value is a ‘0’ bit and rounding the number by truncating the last b bits of the second value or the last b bits of the first value based on the determination.

Abstract: A mechanism for processing, on a hardware accelerator comprising fixed-function circuitry, data according to a neural network process that comprises a neural network with an associated argmax or argmin function. The argmax or argmin function is mapped to a set of elementary neural network operations available to the fixed-function circuitry. The neural network process is then executed using the fixed-function circuitry. The data processed using the neural network process comprises image and/or audio data.

Abstract: A method in a graphics processor searches for a candidate reinsertion for each of a plurality of input nodes in a current bounding volume hierarchy (BVH), which would move the respective input node from an old parent to a new parent, and which would reduce the expected computational cost of searching the BVH for a ray intersection; and updates the current BVH with one or more selected reinsertions selected from among the candidates. In the search for candidate reinsertions, either or both of: a) the new parent is limited to being related to the old parent by an ancestor at no more than a predetermined number of hierarchal levels above the old parent, and/or b) the input nodes are limited to being at or above a hierarchical level a predetermined number of hierarchical levels below the root node.

Abstract: A hardware unit for manipulating data stored in a memory comprises an internal buffer, a memory reading block, configured to read the data from the memory and write the data to the internal buffer. a memory writing block, configured to read the data from the internal buffer and write the data to the memory. The hardware unit optionally also comprises a control channel between the memory reading block and the memory writing block, wherein the memory reading block and the memory writing block are configured to communicate via the control channel to maintain synchronisation between them when writing the data to the internal buffer and reading the data from the internal buffer, respectively. The hardware unit may be configured to apply one or more transformations to multidimensional data in the memory. The hardware unit may be configured to traverse the multidimensional array using a plurality of nested loops.

Abstract: Image element values are determined from a compressed block of image data relating to a reference channel and non-reference channels. Compressed channel data is used to determine an initial data value relating to a channel. A decompressed data value is determined for the non-reference channels by: (i) reading an indication of a compression mode, the compression mode being either a channel decorrelating mode or a non-channel decorrelating mode, (ii) if the compression mode is non-channel decorrelating mode, determining the decompressed data value for the non-reference channel to be the determined initial data value relating to the non-reference channel for the image element value; (iii) if the compression mode is a channel decorrelating mode, determining the decompressed data value for the non-reference channel to be a function of the determined initial data value relating to the non-reference channel and the determined initial data value relating to one of the reference channels.

Abstract: The operation of a GPU is controlled based on one or more deadlines by which one or more GPU tasks must be completed and estimates of the time required to complete the execution of a first GPU task (which is currently being executed) and the time required to execute one or more other GPU tasks (which are not currently being executed). Based on a comparison between the deadline(s) and the estimates, context switching may or may not be triggered.

Abstract: A method of verifying processing logic of a graphics processing unit receives a test task including a predefined set of instructions for execution on the graphics processing unit, the predefined set of instructions being configured to perform a predetermined set of operations on the graphics processing unit when executed for predefined input data. In a test phase, the test task is processed by executing the predefined set of instructions for the predefined input data first and second times at the graphics processing unit so as to, respectively, generate first and second outputs. A fault signal is raised if the first and second outputs do not match.