Patents Assigned to Imagination Technologies Limited
  • Patent number: 12699564
    Abstract: Segment load operations are performed by processing data through an anything-to-anything mux, and sections writing elements to respective storage locations based on corresponding indices of the elements and the storage locations. Once all of the elements are loaded into the correct storage location, each location is read again with the elements of that storage location being sent through the mux, arranged) into the correct order, and written back to the same register.
    Type: Grant
    Filed: January 10, 2025
    Date of Patent: August 4, 2026
    Assignee: Imagination Technologies Limited
    Inventor: Peter Vrabel
  • Patent number: 12700068
    Abstract: A method of rendering an image of a 3-D scene includes rendering a noisy image and obtaining one or more guide channels. For each of a plurality of local neighborhoods, the method comprises: calculating the parameters of a model that approximates the noisy image as a function of the one or more guide channels, and applying the calculated parameters to produce a denoised image. At least one of (i) the noisy image, (ii) the one or more guide channels, and (iii) the denoised image, are stored in a quantized low-bitdepth format.
    Type: Grant
    Filed: May 28, 2024
    Date of Patent: August 4, 2026
    Assignee: Imagination Technologies Limited
    Inventors: Szabolcs Cséfalvay, James Imber, David Walton, Insu Yu
  • Patent number: 12694604
    Abstract: Transforming rendered frames in a graphics processing system to obtain enhanced frames with desired characteristics of a set of target images includes selecting a plurality of shaders, each defined by a parametrized mathematical function arranged to replicate a particular visual characteristic. For each shader, parameters of the parametrized mathematical function have been derived in dependence on a set of target images so that the shader is arranged to impose its respective particular visual characteristic in dependence on an extent to which the particular visual characteristic is exhibited in the target images. The plurality of shaders are combined to form a pipeline, obtaining one or more rendered frames, applying the pipeline to at least a portion of the one or more rendered frames to obtain enhanced frames, and outputting for display the enhanced frames, wherein the enhanced frames exhibit visual characteristics of the target images.
    Type: Grant
    Filed: April 10, 2024
    Date of Patent: July 28, 2026
    Assignee: Imagination Technologies Limited
    Inventors: Arturo Tommaso Salmi, Szabolcs Cséfalvay, James Imber
  • Patent number: 12694191
    Abstract: A circuit for mapping N coordinates to a 1D space receives N input bit-strings representing respective coordinates, which can be of different sizes; produces a grouped bit-string therefrom, in which the bits, including non-data bits, are grouped into groups of bits originating from the same bit position per group; and demultiplexes this into n=1 . . . N demultiplexed bit-strings, and sends each to a respective n-coordinate channel. The nth demultiplexed bit-string includes a respective part of the grouped bit-string that has n coordinate data bits and N-n non-data bits per group, and all other groups filled with null bits. Each but the N-coordinate channel includes bit-packing circuitry which packs down the respective demultiplexed bit-string by removing the non-data bits, and removing the same number of bits per group from the null bit.
    Type: Grant
    Filed: April 30, 2024
    Date of Patent: July 28, 2026
    Assignee: Imagination Technologies Limited
    Inventor: Tijmen Spreij
  • Patent number: 12682556
    Abstract: A method and system is provided for culling hidden objects in a tile-based graphics system before they are indicated in a display list for a tile. A rendering space is divided into a plurality of regions which may for example be a plurality of tiles or a plurality of areas into which one or more tiles are divided. Depth thresholds for the regions, which are used to identify hidden objects for culling, are updated when an object entirely covers a region and in dependence on a comparison between a depth value for the object and the depth for the region. For example, if the depth threshold is a maximum depth threshold, the depth threshold may be updated if an object entirely covers the tile and the maximum depth value of the object is less than the maximum depth threshold.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: July 14, 2026
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, John W. Howson, Simon Fenney
  • Patent number: 12682435
    Abstract: Methods and processing modules apply adaptive sharpening, for a block of input pixels for which processing is performed, to determine a block of output pixels. A block of non-sharp processed pixels is obtained based on the block of input pixels, the block of non-sharp processed pixels being for representing a non-sharp version of the block of output pixels. A block of sharp processed pixels is obtained based on the block of input pixels, the block of sharp processed pixels being for representing a sharp version of the block of output pixels. One or more indications of contrast for the block of input pixels is determined. Each of the output pixels of the block of output pixels is determined by performing a respective weighted sum of: (i) a corresponding non-sharp processed pixel in the block of non-sharp processed pixels and (ii) a corresponding sharp processed pixel in the block of sharp processed pixels.
    Type: Grant
    Filed: September 27, 2023
    Date of Patent: July 14, 2026
    Assignee: Imagination Technologies Limited
    Inventors: James Imber, Joseph Heyward, Kristof Beets
  • Patent number: 12682543
    Abstract: A method and processor for retrieving a block of data items, each being associated with a coordinate for each of dimensions of a stored data array. A data processing unit detects that the coordinates are axis-aligned. In response to detecting that the coordinates are axis-aligned, the following are sent to a data load unit: only one coordinate for a first dimension for each line of data items aligned in the first dimension within the block, and only one coordinate for a second dimension for each line of data items aligned in the second dimension within the block, the second dimension being orthogonal to the first dimension. The data load unit: (i) processes the coordinates to generate addresses of data array elements to be fetched from the stored data array, (ii) fetches data array elements using the generated addresses, (iii) determines data item values based on the fetched data array elements, and (iv) outputs the data item values.
    Type: Grant
    Filed: December 22, 2023
    Date of Patent: July 14, 2026
    Assignee: Imagination Technologies Limited
    Inventors: Aroun Demeure, William Thomas, Alexander Hoffmann, Arturo Barrabes Castillo
  • Patent number: 12670662
    Abstract: A method performed by a graphics processor obtains a starting bounding volume hierarchy (BVH), being a data structure comprising nodes representing different 3D regions of space in a modelled environment, the data structure comprising a tree in which the nodes are arranged hierarchically from a root node down to a plurality of leaf nodes, wherein the region modelled by each leaf node encompasses at least one primitive or part of a primitive. The method further comprises performing one or more iterations, starting with a first iteration which starts with the starting BVH as a current BVH, which search for candidate reinsertions to move input nodes to new parents in the tree to reduce expected computational cost.
    Type: Grant
    Filed: March 25, 2023
    Date of Patent: June 30, 2026
    Assignee: Imagination Technologies Limited
    Inventor: Joseph John Davison
  • Patent number: 12664434
    Abstract: Methods and systems for identifying quantisation parameters for a Deep Neural Network (DNN). The method includes determining an output of a model of the DNN in response to training data, the model of the DNN comprising one or more quantisation blocks configured to transform a set of values input to a layer of the DNN prior to processing the set of values in accordance with the layer, the transformation of the set of values simulating quantisation of the set of values to a fixed point number format defined by one or more quantisation parameters; determining a cost metric of the DNN based on the determined output and a size of the DNN based on the quantisation parameters; back-propagating a derivative of the cost metric to one or more of the quantisation parameters to generate a gradient of the cost metric for each of the one or more quantisation parameters; and adjusting one or more of the quantisation parameters based on the gradients.
    Type: Grant
    Filed: March 4, 2024
    Date of Patent: June 23, 2026
    Assignee: Imagination Technologies Limited
    Inventor: Szabolcs Cséfalvay
  • Patent number: 12657056
    Abstract: A method of activating scheduling instructions within a parallel processing unit includes checking if an ALU targeted by a decoded instruction is full by checking a value of an ALU work fullness counter stored in the instruction controller and associated with the targeted ALU. If the targeted ALU is not full, the decoded instruction is sent to the targeted ALU for execution and the ALU work fullness counter associated with the targeted ALU is updated. If, however, the targeted ALU is full, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state. When an ALU changes from being full to not being full, the scheduler is triggered to re-activate an oldest scheduled task waiting for the ALU by removing the oldest scheduled task from the non-active state.
    Type: Grant
    Filed: January 8, 2024
    Date of Patent: June 16, 2026
    Assignee: Imagination Technologies Limited
    Inventors: Simon Nield, Yoong-Chert Foo, Adam de Grasse, Luca Iuliano
  • Patent number: 12657805
    Abstract: Ray tracing systems and computer-implemented methods for generating a hierarchical acceleration structure for intersection testing in a ray tracing system. Nodes of the hierarchical acceleration structure are determined, wherein each of the nodes represents a region in a scene, and wherein the nodes are linked to form the hierarchical acceleration structure. Data is stored representing the hierarchical acceleration structure including data defining the regions represented by a plurality of the nodes of the hierarchical acceleration structure. At least one node is an implicitly represented node, wherein data defining a region represented by an implicitly represented node is not explicitly included as part of the stored data but can be inferred from the stored data.
    Type: Grant
    Filed: November 6, 2023
    Date of Patent: June 16, 2026
    Assignee: Imagination Technologies Limited
    Inventors: Gregory Clark, Steven J. Clohset
  • Patent number: 12657827
    Abstract: Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.
    Type: Grant
    Filed: July 30, 2024
    Date of Patent: June 16, 2026
    Assignee: Imagination Technologies Limited
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 12651157
    Abstract: Methods and systems of generating gradients of a loss metric for a neural network (NN) with respect to weights of a convolution layer of the NN, the convolution layer of the NN configured to receive an input tensor of input values and a weight tensor of weights, and generate an output tensor of output values.
    Type: Grant
    Filed: March 19, 2022
    Date of Patent: June 9, 2026
    Assignee: Imagination Technologies Limited
    Inventors: Aria Ahmadi, Cagatay Dikici
  • Patent number: 12646217
    Abstract: A block of sub-primitive presence indications for use in intersection testing in a rendering system is compressed into a block of compressed data. Spatial decorrelation is performed to determine spatially decorrelated presence indications by (i) determining a predicted value for the presence indication based on one or more other presence indications in the line, and (ii) replacing the presence indication with a value of a difference between the presence indication and the determined predicted value for the presence indication. For each line of presence indications in a second dimension within the block, for one or more of the presence indications in the line: (i) a predicted value for the presence indication is determined based on one or more other presence indications in the line, and (ii) the presence indication is replaced with a value of a difference between the presence indication and the determined predicted value for the presence indication.
    Type: Grant
    Filed: May 30, 2023
    Date of Patent: June 2, 2026
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 12639182
    Abstract: A method of processing instructions at a processing unit having a parallel processing engine. During a mission cycle, a first set of mission operand values is processed in accordance with a mission instruction at a first processing instance to generate a first mission output. In parallel, a second set of mission operand values is processed in accordance with the mission instruction at a second processing instance to generate a second mission output. During a test cycle, a first set of test operand values is processed in accordance with a test instruction at the first processing instance to generate a first test output, and in parallel, a second set of test operand values is processed in accordance with the test instruction at the second processing instance to generate a second test output, where the first set of test operand values is the same as the second set of test operand values.
    Type: Grant
    Filed: October 6, 2024
    Date of Patent: May 26, 2026
    Assignee: Imagination Technologies Limited
    Inventors: Daniel Wilkinson, Ian King
  • Patent number: 12638988
    Abstract: Methods and storage unit allocators for allocating one or more portions of a storage unit to a plurality of tasks for storing at least two types of data. The method includes receiving a request for one or more portions of the storage unit to store a particular type of data of the at least two types of data for a task of the plurality of tasks; associating the request with one of a plurality of virtual partitionings of the storage unit based on one or more characteristics of the request, each virtual partitioning allotting none, one, or more than one portion of the storage unit to each of the at least two types of data; and allocating the requested one or more portions of the storage unit to the task from the none, one, or more than one portion of the storage unit allotted to the particular type of data in the virtual partitioning associated with the request.
    Type: Grant
    Filed: November 4, 2024
    Date of Patent: May 26, 2026
    Assignee: Imagination Technologies Limited
    Inventor: Ian King
  • Patent number: 12633043
    Abstract: Coarse depth testing is performed in a graphics processing system having a rendering space divided into a plurality of tiles. A depth range for a tile identifies a depth range based on primitives previously processed. A determination is made based on the depth range as to whether all or a portion of a primitive is hidden in the tile. If at least a portion is not hidden in the tile, a determination is made as to whether the primitive or a primitive fragment thereof has better depth than the primitives previously processed. If so, the primitive or primitive fragment is identified as not requiring a read of a depth buffer to perform full resolution depth testing, such that a determination that at least a portion of the primitive is hidden in the tile causes full resolution depth testing not to be performed on at least that portion of the primitive.
    Type: Grant
    Filed: March 4, 2024
    Date of Patent: May 19, 2026
    Assignee: Imagination Technologies Limited
    Inventors: Lorenzo Belli, Robert Brigg
  • Patent number: 12625539
    Abstract: A method of controlling a memory device in which the memory device has a normal mode in which the memory device is operable, and a power save mode in which the memory device is inoperable and consumes lower power than the normal mode. The method includes determining a metric based on the time spent by the memory device in at least one previous inactive period. The method further includes comparing the metric with a threshold. Further the method includes in response to determining that the metric is lower than the threshold causing the memory device to remain in the normal mode throughout a subsequent inactive period.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: May 12, 2026
    Assignee: Imagination Technologies Limited
    Inventors: Zhi Gao, Suneel Varma Uppalapati Venkata
  • Patent number: 12625920
    Abstract: An aspect includes an apparatus for evaluating a mathematical function at an input value. The apparatus includes a selector for selecting a mathematical function, an input for a value at which to evaluate the function, an identifier for identifying an interval containing the input value. The interval is described by at least one polynomial function. At least one control point representing the polynomial function is retrieved from at least one look up table, and the polynomial function can be derived from the control points. The function is evaluated at the input value and an output of the evaluation is used as a value of the function at that input value.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: May 12, 2026
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 12620161
    Abstract: A computer implemented method converts ray data for a ray into a ray representative, wherein the ray representative is a compressed representation of the ray data, and wherein the ray data comprises three direction components and three position components for the ray. The method comprises identifying which of the three direction components of the ray data has the greatest magnitude, and defining the axis of the identified direction component as the major axis of the ray. The method further comprises determining a translated position on the ray at which the position component along the major axis is zero, and rescaling the three direction components of the ray so that the magnitude of the direction component along the major axis is one. The ray representative comprises: (i) the two position components of the translated position along the axes which are not the major axis, and (ii) the two rescaled direction components along the axes which are not the major axis.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: May 5, 2026
    Assignee: Imagination Technologies Limited
    Inventors: Peter Smith-Lacey, Simon Fenney