Patents Assigned to Imagination Technologies Limited
  • Patent number: 11922321
    Abstract: Methods and systems for identifying quantisation parameters for a Deep Neural Network (DNN). The method includes determining an output of a model of the DNN in response to training data, the model of the DNN comprising one or more quantisation blocks configured to transform a set of values input to a layer of the DNN prior to processing the set of values in accordance with the layer, the transformation of the set of values simulating quantisation of the set of values to a fixed point number format defined by one or more quantisation parameters; determining a cost metric of the DNN based on the determined output and a size of the DNN based on the quantisation parameters; back-propagating a derivative of the cost metric to one or more of the quantisation parameters to generate a gradient of the cost metric for each of the one or more quantisation parameters; and adjusting one or more of the quantisation parameters based on the gradients.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: March 5, 2024
    Assignee: Imagination Technologies Limited
    Inventor: Szabolcs Csefalvay
  • Patent number: 11922536
    Abstract: Input/output filter units for use in a graphics processing unit include a first buffer configured to store data received from, and output to, a first component of the graphics processing unit; a second buffer configured to store data received from, and output to, a second component of the graphics processing unit; a weight buffer configured to store filter weights; a filter bank configurable to perform any of a plurality of types of filtering on a set of input data, the plurality of types of filtering comprising one or more texture filtering types and one or more pixel filtering types; and control logic configured to cause the filter bank to: (i) perform one of the plurality of types of filtering on a set of data stored in one of the first and second buffers using a set of weights stored, and (ii) store the results of the filtering in one of the first and second buffers.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: March 5, 2024
    Assignee: Imagination Technologies Limited
    Inventor: Kristof Beets
  • Patent number: 11922534
    Abstract: A method and system for generating and shading a computer graphics image in a tile based computer graphics system is provided. Geometry data is supplied and a plurality of primitives are derived from the geometry data. One or more modified primitives are then derived from at least one of the plurality of primitives. For each of a plurality of tiles, an object list is derived including data identifying the primitive from which each modified primitive located at least partially within that tile is derived. Alternatively, the object list may include data identifying each modified primitive located at least partially within that tile. Each tile is then shaded for display using its respective object list.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: March 5, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Steven J. Fishwick, John W. Howson
  • Patent number: 11922555
    Abstract: Methods and tiling engines for tiling primitives in a tile based graphics processing system in which a rendering space is divided into a plurality of tiles. The method includes generating a multi-level hierarchy of tile groups, each level of the multi-level hierarchy comprising one or more tile groups comprising one or more of the plurality of tiles; receiving a plurality of primitive blocks, each primitive block comprising geometry data for one or more primitives; associating each of the plurality of primitive blocks with one or more of the tile groups up to a maximum number of tile groups such that if at least one primitive of a primitive block falls, at least partially, within the bounds of a tile, the primitive block is associated with at least one tile group that includes that tile; and generating a control stream for each tile group based on the associations, wherein each control stream comprises a primitive block entry for each primitive block associated with the corresponding tile group.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: March 5, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Diego Jesus, John W. Howson, Panagiotis Velentzas, Robert Brigg, Xile Yang
  • Patent number: 11914514
    Abstract: A coherency manager for receiving snoop requests addressed in a physical address space, the snoop requests relating to a cache memory addressable using a virtual address space, the cache memory having a plurality of coherent cachelines, the coherency manager comprising: a reverse translation module configured to maintain a mapping from physical addresses to virtual addresses for each coherent cacheline held in the cache memory; and a snoop processor configured to: receive a snoop request relating to a physical address; in response to the received snoop request, determine whether the physical address is mapped to a virtual address in the reverse translation module; and process the snoop request in dependence on that determination.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: February 27, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Martin John Robinson, Mark Landers
  • Patent number: 11915363
    Abstract: A tag buffer implements a tag buffer stage of a rasterization phase in a tile-based rendering graphics processing system having a rendering space sub-divided into a plurality of tiles to which primitives can be associated. A buffer stores an identifier that identifies a visible primitive fragment at each sample position of a tile of the plurality of tiles. A look-up table stores an entry for transformed primitive blocks that indicates whether the tag buffer has received information identifying a primitive fragment associated with that transformed primitive block.
    Type: Grant
    Filed: May 28, 2023
    Date of Patent: February 27, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Robert Brigg, John W. Howson, Xile Yang
  • Patent number: 11915345
    Abstract: Methods and hardware for cube mapping comprise receiving fragment coordinates for an input block of fragments and texture instructions for the fragments and then determining, based on gradients of the input block of fragments, whether a first mode of cube mapping or a second mode of cube mapping is to be used, wherein the first mode of cube mapping performs calculations at a first precision for a subset of the fragments and calculations for remaining fragments at a second, lower, precision and the second mode of cube mapping performs calculations for all fragments at the first precision. Cube mapping is then performed using the determined mode and the gradients, wherein if the second mode is used and more than half of the fragments in the input block are valid, the cube mapping is performed over two clock cycles.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: February 27, 2024
    Assignee: Imagination Technologies Limited
    Inventor: Rostam King
  • Patent number: 11915455
    Abstract: Methods and compression units for compressing a block of image data, the block of image data comprising a plurality of image element values, the image element values being divisible into at least a first value and a second value such that the block of image data comprises a two-dimensional block of first values, the method comprising: compressing a first data set comprising all or a portion of the two-dimensional block of first values in accordance with a first fixed-length compression algorithm to generate a first compressed block by: identifying common base information for the first data set; and identifying a fixed-length parameter for each first value in the first data set, the fixed-length parameter being zero, one or more than one bits in length; and forming a compressed block for the block of image data based on the first compressed block.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: February 27, 2024
    Assignee: Imagination Technologies Limited
    Inventor: Xile Yang
  • Patent number: 11915397
    Abstract: A method of rendering an image of a 3-D scene includes rendering a noisy image; and obtaining one or more guide channels. For each of a plurality of local neighbourhoods, the method comprises: calculating the parameters of a model that approximates the noisy image as a function of the one or more guide channels, and applying the calculated parameters to produce a denoised image. Tiling is used when calculating the parameters of the model.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: February 27, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Szabolcs Csefalvay, James Imber, David Walton, Insu Yu
  • Patent number: 11916798
    Abstract: A method of estimating available bandwidth for a network comprising a transmitting device and a receiving device, the method comprising: transmitting a media packet stream over the network to the receiving device, the media packets comprising media data for streaming media at the receiving device; transmitting one or more probe packets over the network so as to test the available bandwidth of the network, wherein the probe packets comprise duplicate data of the media packet stream; and determining, during transmission of the probe packets, a measure of network bandwidth availability in dependence on one or more metrics associated with receiving the media packet stream at the receiving device.
    Type: Grant
    Filed: January 25, 2023
    Date of Patent: February 27, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Senthil Kumar Mani, Bala Manikya Prasad Puram
  • Patent number: 11915358
    Abstract: A method and system for performing safety-critical rendering of a frame in a tile based graphics processing system. Geometry data for the frame is received, including data defining a plurality of primitives representing a plurality of objects in the frame. A definition of a region in the frame is received, the region being associated with one or more primitives among the plurality of primitives. Verification data is received that associates one or more primitives with the region in the frame. The frame is rendered using the geometry data and the rendering of the frame is controlled using the verification data, so that the rendering excludes, from the frame outside the region, the primitives identified by the verification data.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: February 27, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Jamie Broome, Ian King
  • Patent number: 11915396
    Abstract: A pixel filter has a filter module that performs a first recursive filter operation in a first direction through a sequence of pixels to form a first filtered pixel value for each pixel, and performs a second recursive filter operation in a second direction through the sequence of pixels to form a second filtered pixel value for each pixel, the first and second recursive filter operations forming a respective filtered pixel value for a given pixel in dependence on the pixel value at that pixel and the filtered pixel value preceding that pixel in their respective direction of operation. The filtered pixel value of the preceding pixel is scaled by a measure of similarity between data associated with that pixel and its preceding pixel. Filter logic combines the first and second filtered pixel values formed by the first and second recursive filter operations to generate a filter output for the pixel, for each pixel of the sequence.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: February 27, 2024
    Assignee: Imagination Technologies Limited
    Inventor: Szabolcs Csefalvay
  • Patent number: 11907830
    Abstract: Hardware for implementing a Deep Neural Network (DNN) having a convolution layer. A plurality of convolution engines each perform a convolution operation by applying a filter to a data window. Each of the plurality of convolution engines includes multiplication logic that combines a weight of a filter with a respective data value of a data window; control logic that receives configuration information identifying a set of filters for operation on a set of data windows at the plurality of convolution engines; determines a sequence of convolution operations for evaluation at the multiplication logic; requests weights and data values for at least partially applying a filter to a data window; and causes the multiplication logic to combine the weights with their respective data values. Accumulation logic accumulates the results of a plurality of combinations performed by the multiplication logic to form an output for a convolution operation of the determined sequence.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: February 20, 2024
    Assignee: Imagination Technologies Limited
    Inventor: Christopher Martin
  • Patent number: 11908106
    Abstract: Data processing systems (e.g. image processing systems) and methods are provided for processing a stream of data values (e.g. pixel values). The image processing system comprises a processing module configured to: receive a plurality of pixel values; and implement processing of a particular pixel value by operating on a particular subset of the received pixel values, by: defining a set of one or more groups into which pixel values within the particular subset can be grouped; classifying each of the pixel values within the particular subset into one of the groups of the set of one or more groups based on the value of that pixel value; processing the particular pixel value using one or more of the pixel values of the particular subset in dependence on the classification of the pixel values of the particular subset into the one or more groups; and outputting the processed particular pixel value.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: February 20, 2024
    Assignee: Imagination Technologies Limited
    Inventor: Timothy Lee
  • Patent number: 11900036
    Abstract: Methods and systems for verifying a property of an integrated circuit hardware design. The method includes formally verifying, using a formal verification tool, that the property is true for the hardware design under a constraint that an instantiation of the hardware design transitions to a quiescent state at a symbolic time.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: February 13, 2024
    Assignee: Imagination Technologies Limited
    Inventor: Reinald Cruz
  • Patent number: 11900543
    Abstract: A tessellation method uses both vertex tessellation factors and displacement factors defined for each vertex of a patch, which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves calculating a vertex tessellation factor for each corner vertex in one or more input patches. Tessellation is then performed on the plurality of input patches using the vertex tessellation factors. The tessellation operation involves adding one or more new vertices and calculating a displacement factor for each newly added vertex. A world space parameter for each vertex is subsequently determined by calculating a target world space parameter for each vertex and then modifying the target world space parameter for a vertex using the displacement factor for that vertex.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: February 13, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 11900503
    Abstract: A multicore graphics processing unit (GPU) and a method of operating a GPU are provided. The GPU comprises at least a first core and a second core. At least one of the cores in the multicore GPU comprises a master unit configured to distribute geometry processing tasks between at least the first core and the second core.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: February 13, 2024
    Assignee: Imagination Technologies Limited
    Inventor: Ian King
  • Patent number: 11900122
    Abstract: Methods and parallel processing units for avoiding inter-pipeline data hazards identified at compile time. For each identified inter-pipeline data hazard the primary instruction and secondary instruction(s) thereof are identified as such and are linked by a counter which is used to track that inter-pipeline data hazard. When a primary instruction is output by the instruction decoder for execution the value of the counter associated therewith is adjusted to indicate that there is hazard related to the primary instruction, and when primary instruction has been resolved by one of multiple parallel processing pipelines the value of the counter associated therewith is adjusted to indicate that the hazard related to the primary instruction has been resolved.
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: February 13, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Luca Iuliano, Simon Nield, Yoong-Chert Foo, Ollie Mower
  • Patent number: 11893754
    Abstract: Methods and image processing systems are provided for determining a dominant gradient orientation for a target region within an image. A plurality of gradient samples are determined for the target region, wherein each of the gradient samples represents a variation in pixel values within the target region. The gradient samples are converted into double-angle gradient vectors, and the double-angle gradient vectors are combined so as to determine a dominant gradient orientation for the target region.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: February 6, 2024
    Assignee: Imagination Technologies Limited
    Inventor: Ruan Lakemond
  • Patent number: 11887244
    Abstract: A system and method for performing intersection testing of rays in a ray tracing system. The ray tracing system uses a hierarchical acceleration structure comprising a plurality of nodes, each identifying one or more elements for intersection testing. The system defines and updates progress information that identifies, for a ray, leaf nodes of the hierarchical acceleration structure which identify elements for which it is not yet known whether or not the ray interests.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: January 30, 2024
    Assignee: Imagination Technologies Limited
    Inventor: Daniel Barnard