Abstract: A method of forming at least one bonding structure may be provided. A ball may be formed on the front end of a wire outside a capillary. The capillary may be moved downwardly to form a preliminary compressed ball on a first pad using the ball. The capillary may be moved upwardly to form a neck portion on the preliminary compressed ball using the preliminary compressed ball and the wire. The capillary may be moved obliquely and downwardly to form a compressed ball. The capillary may extend the wire from the compressed ball to a second pad.

Abstract: Disclosed are a light guide member and a keypad assembly including the same. The light guide member includes a light guide plate for guiding light propagated inside, and at least one recess formed in a direction perpendicular to a direction of guidance of light coupled to the inside of the light guide plate so that light guided by the light guide plate is reflected to the light guide plate. The keypad assembly includes a keypad having at least one key button and an elastic sheet fixing the key button, a light guide member positioned beneath the keypad, the light guide member having a light guide plate for guiding light coupled to an inside and at least one recess for reflecting light guided by the light guide plate to the light guide plate, and a switch pad positioned beneath the light guide member so as to establish an electric contact when the key button is pressed.

Abstract: The present invention provides a liquid crystal display having excellent visibility. A thin film transistor array panel is provided, which includes: gate lines formed on an insulating substrate; data lines insulated from the gate lines and intersecting the gate lines; first pixel electrodes disposed on pixel areas defined by intersections of the gate lines and the data lines; first thin film transistors, each having three terminals connected to one of the gate lines, one of the data lines, and one of the first pixel electrodes; second pixel electrodes disposed on the pixel areas and capacitively coupled to the first pixel electrodes; and second thin film transistors, each having three terminals connected to a previous gate line, a storage electrode line or one of the data lines, and one of the second pixel electrodes.

Abstract: An integrated circuit device may include a main clock signal input pad configured to receive a main clock signal having a main clock frequency, a high speed clock signal input pad configured to receive a high speed clock signal having a high speed clock frequency greater than the main clock frequency, a frequency divider, and a phase controller. The frequency divider may be configured to generate a plurality of preliminary internal clock signals responsive to the high speed clock signal wherein each of the preliminary internal clock signals has the same main clock frequency and a different phase.

Abstract: Systems that employs an adaptable front end for determining a file-type to associate with the output from a source application and for processing the output, as a function of the file type, to generate a display list that is representative of objects and shapes that represent components within the visual presentation of the data. The display list is then processed by a rendering engine, which may be located on an embedded device. The rendering engine processes the components contained within the display list to render an image of the source application's output that may be presented on the display of the device. As will be described below, the adaptable front end determines the file structure of the source being processed, thereby providing a device that may operate with a plurality of different file types, and source applications.

Abstract: Embodiments of the invention provide a digital-to-analog converter (DAC) that is configured to process upper data bits, a control data bit, and a lower data bit using two decoders and a control logic. The resulting DAC provides high resolution output using a minimum circuit area. Embodiments of the invention also provide a sample and hold circuit for a DAC that reduces the effects of parasitic capacitance at the input of an operational amplifier (OP-AMP).

Abstract: Provided are a non-volatile memory device and a method of operating the non-volatile memory device. The non-volatile memory device includes a switching device and a storage node connected to the switching device, wherein the storage node comprises: a first electrode connected to the switching device; a chalcogenide material layer formed on the first electrode; and a second electrode formed on the chalcogenide material layer, and one of the first and second electrodes comprises an electrode contact layer formed adjacent to a limited region of the chalcogenide material layer, and a property of the electrode region adjacent to the chalcogenide material layer is changed reversibly according to the direction in which a current is applied, thereby changing between a high resistance state and a low resistance state.

Abstract: A lighting device and a display device are provided. The lighting device includes: a light source; a light dividing member; and a beam shaper. The light dividing member includes a light receiving surface, on which light is incident, and divides the incident light into a plurality of light beam groups each having a predetermined width and interval therebetween. The beam shaper is disposed between the light source and the light dividing member. Light from the light source is incident on the beam shaper, and light emitted form the beam shaper is parallel and has a cross-sectional shape corresponding to the shape of the light receiving surface of the light dividing member.

Abstract: Provided is an image sensor including a sensing transistor having two gates and a method of operating the image sensor. The image sensor may include a photoelectric conversion device, a sensing transistor which may have a first gate connected to a floating diffusion region in which charges generated from the photoelectric conversion region are stored and a second gate separated from the first gate, a reset transistor that may be connected to the floating diffusion region and may reset a potential of the floating diffusion region, a control voltage source that may supply a control applied to the second gate, and a column output line which may be connected to a source of the sensing transistor.

Abstract: Provided is a method in which a tracker configures a notification condition on the basis of an authorization policy predetermined by a trackee so that a location information server provides a customized location tracking service according to the notification condition. The method includes: (a) registering an authorization policy of a trackee in order to determine whether a location tracking service requested by a tracker will be accepted; (b) configuring a customized location information notification condition by a tracker; (c) requesting the customized location tracking service by the tracker; and (d) providing the customized location tracking service by a location information server on the basis of the configured authorization policy and the customized location information notification condition.

Abstract: Provided is a non-volatile memory device including first and second, vertically stacked semiconductor substrates, a plurality of non-volatile memory cell transistors formed in a row on the first and second semiconductor substrates, and a plurality of word lines connected to gates of the plurality of non-volatile memory cell transistors. The plurality of non-volatile memory cell transistors are grouped into two or more memory cell blocks, such that a first voltage is applied to the first semiconductor substrate including a first memory cell block to be erased, and either (1) a second voltage less than the first voltage and greater than 0V is applied to the second semiconductor substrate not including the first memory cell block, or (2) the second semiconductor substrate not including the first memory cell block is allowed to electrically float.

Abstract: The semiconductor integrated circuit device includes a plurality of decoupling cells that suppress power noise respectively, a plurality of power switches that connect the decoupling cells to a power line respectively, and a control circuit that controls the number of power switches selected from among the plurality of power switches and to be turned on according to power noise to be changed according to the operation state of each of internal circuits driven by a power supplied from the power line.

Abstract: Disclosed is a portable terminal capable of enhancing compatibility with a hearing aid. The portable terminal comprises a terminal case having a sound hole thereon; a receiver installed inside the sound hole; and a reflection unit disposed between the terminal case and the receiver, for reflecting an electromagnetic wave radiated from an interior or a surface of the terminal case so as to minimize leakage of the electromagnetic wave to outside of the terminal case.

Abstract: A fuel gauge for power supplies having a voltage pre-regulator; a main voltage regulator; a current sense resistor; an integrator with an op amp and capacitor, wherein the integrator receives power from the main voltage regulator, and receives a voltage proportional to current from the current sense resistor; a microprocessor with data storage and a hysteresis circuit, wherein the microprocessor operates in a low power state until activated by the resistor and the microprocessor converts the voltage proportional to current to a monotonic uni-polar representation of an aggregate number of electrons; a resistor disposed between the integrator and the microprocessor for activating the microprocessor from the low power state prior to saturation of the integrator with the voltage proportional to current; and a reset circuit disposed between the microprocessor and the integrator for resetting the monotonic uni-polar representation of an aggregate number of electrons to zero.

Abstract: A memory expansion pack, which includes a memory for storing content, an FM receiver, an ear jack, and a controller, is connected with a portable terminal through a connector of the pack to provide content to the terminal. Under the control of the controller, content stored in the memory and audio data, which is received through the FM receiver from an external device over a set frequency channel, is transmitted to the terminal. When the ear jack is connected with the external output device, it outputs the content through the external output device. When the ear jack is connected with a device, such as a PC, the ear jack downloads content from the PC. The memory expansion pack allows the user to provide and use a large amount of various content. The pack can also provide high quality services, overcoming the limited memory capacity of portable terminals, and reduce the cost of wireless data communication.

Abstract: Disclosed is a multiprocessor apparatus including a plurality of processors connected to a common bus, a co-processor provided in common to the processors, an arbitration circuit that arbitrates contention among the processors with respect to use of a resource in the co-processor through a tightly coupled bus by the processors and a multiplexer coupled to the arbitration circuit, coupled to the processors through a local buses, and coupled to the co-processor through the local buses to transfer the commands received from the respective processors to the co-processor in accordance with a permission signal output by the arbitration circuit.

Abstract: In an assembly of a seat foam and a sensor mat, the seat foam has at least one incision and the sensor mat has at least one anchor tab adapted to be inserted into the at least one incision, thereby securely holding the sensor mat on a surface of the seat foam, where the seat foam includes at least one retaining element at the incision for retaining the anchor tab in the incision.

Abstract: Disclosed is a semiconductor memory system and wear-leveling method thereof. The semiconductor memory system is comprised of a nonvolatile memory including a plurality of logic blocks each of which is divided into a plurality of entries, a file system detecting a type of data to be stored and allocating the logic block or the entry for storing the data in accordance with the data type, and a translation layer leveling wearing degrees over the logic blocks or the entries in accordance with the data type.