Abstract: Spectral imaging systems are used to gather spectral image data on earthen material moving within an earthen material processing system, such as a mineral processing system or cement plant. Machine learning models such as 3D convolutional neural networks may be utilized to process the spectral image data to determine or classify one or more characteristics of the earthen material, such as ore grade, mineral alteration(s), moisture content, lithology and/or mineralogy. Such earthen material characteristics, or classifications thereof, may then be utilized to automatically control one or more operational characteristics of the earthen material processing system, such as rotational speed of milling equipment or flow rates of water or chemicals added to milling equipment or mineral concentration systems.

Abstract: A sensor event detection system including a motion capture element and another sensor. The sensor captures values associated with an orientation, position, velocity and acceleration and recognizes an event within the data to determine event data. Uses other values associated with a temperature, humidity, wind and elevation, i.e., environmental and physiological sensors and correlates the data or event data with the other values to determine a type of event or true event or a false positive event, or a type of equipment the motion capture element is coupled with, or a type of activity indicated by the data or event data and transmits the data or event data associated with the event.

Abstract: A method and system are provided for monitoring operations of heavy equipment having an operating implement configured to excavate a load from a mine face. The method involves: capturing a plurality of images during an operating cycle of the heavy equipment; processing the plurality of images through an activity classifier model, the activity classifier model including a neural network having been configured and trained for generating an activity label based on a sequence of images in the plurality of images, the activity label associating the sequence of images with at least one stage of a plurality of stages making up the operating cycle; and performing at least one analysis using the sequence of images associated with the at least one stage, the at least one analysis including an analysis of the operating implement, an analysis of the load, and/or an analysis of the mine face.

Abstract: Exemplary light control devices and methods provide a regional variation of visual information and sampling (“V-VIS”) of an ocular field of view that improves or stabilizes vision, ameliorates a visual symptom, reduces the rate of vision loss, or reduces the progression of an ophthalmic or neurologic condition, disease, injury or disorder. The V-VIS devices and methods generate a moving aperture effect anterior to a retina that samples and delivers to the retina environmental light from an ocular field of view at a sampling rate between 50 hertz and 50 kilohertz. Certain of these V-VIS devices and methods may be combined with augmented or virtual reality, vision measurement, vision monitoring, or other therapies including, but not limited to, pharmacological, gene, retinal replacement and stem cell therapies.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller executes a first firmware, sets a value of a lock indicator to a first value in the first firmware, and sequentially receive a first firmware update command and a second firmware update command. In response to the first firmware update command, the memory controller receives file of a second firmware. When determining that a version number of the second firmware is set to a specific version number, the memory controller sets the value of the lock indicator to a second value. In response to the second firmware update command, the memory controller receives a file of a third firmware. When the value of the lock indicator is set to the second value, the memory controller performs a firmware update procedure to the first firmware with the third firmware.

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Abstract: A motion platform apparatus (100) for vehicle simulation comprises a payload platform (134) having peripheral elevation sites (136, 138, 140). The apparatus (100) also comprises abase stage (102) having peripheral anchoring sites, and linkages (110, 112, 114) configured to couple the peripheral anchoring sites to the peripheral elevation sites (136, 138, 140) respectively, the linkages (110, 112, 114) comprising a first linkage (110). The first linkage (110) comprises a first arm (116) operably coupled at a first end thereof by a spherical joint (128) to a second arm (122) at a first end thereof. The first arm (116) is operably coupled at a second end thereof to an anchoring site of the peripheral anchoring sites by a first revolute joint (132). The second arm (122) is operably coupled at a second end thereof to an elevation site (136) of the peripheral elevation sites (136, 138, 140) by a second revolute joint (146).

Abstract: The invention relates to a method and an apparatus for executing Structural Query Language (SQL) instructions in a Solid-state Storage Device (SSD). The apparatus includes: a processing unit; and a database accelerator. The processing unit is arranged operably to obtain an SQL query from a host side. The database accelerator is arranged operably to parse the SQL query according an SQL syntax tree to generate a series of table tasks to execute; and during the execution of the table tasks, read tables from a flash module through the processing unit, generate intermediate tables and sub-tables based on the read tables, and perform an arithmetic computation, a logical computation or both on a specific field in one intermediate table to generate a final dataset. The processing unit is arranged operably to reply to the host side with the final dataset.

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller executes a first firmware, sets a value of a lock indicator to a first value and receives a first firmware update command in the first firmware. In response to the first firmware update command, the memory controller receives a file of a second firmware. When a version number of the second firmware is a specific version number, the memory controller sets the value of the lock indicator to a second value. When the version number of the second firmware is not a specific version number, the memory controller performs an unlocked firmware update procedure when the value of the lock indicator is set to the second value, and performs a locked firmware update procedure when the value of the lock indicator is not set to the second value.

Abstract: Methods and apparatus to improve or restore vision by causing a rebooting of the visual system of an eye with modification of visual search, sampling and stimulation away from the preferred retinal locus of fixation of an eye to enhance neural integration and perception of visual information from within the field of view are described herein. Some embodiments cause transient, reversible or repeatable redirection of environmental light away from the preferred retinal locus of fixation of an eye to multiple retinal locations that are not the preferred retinal locus of fixation. Some embodiments reduce exposure of environmental light at the preferred retinal locus of fixation of an eye for a determinable interval at a determinable rate. Some embodiments cause a defocusing of environmental light at the preferred retinal locus of fixation in an eye with a visual impairment or loss.

Abstract: A lifting column includes a drive unit, a lifting tube, and a transmission assembly. The lifting tube includes a first tube, a second tube, a third tube, a fourth tube, and a fifth tube. The transmission assembly includes a first screw rod, a second screw rod, a third screw rod, and a fourth screw rod. The drive unit is in transmission fit with the first screw rod and drives the first screw rod to rotate. A lower end of the second screw rod has a first nut in transmission with the first screw rod, a lower end of the third screw rod has a second nut in transmission with the second screw rod, a lower end of the fourth screw rod has a third nut in transmission with the third screw rod, and a lower end of the first tube has a fourth nut in transmission with the fourth screw rod.

Abstract: A method of a flash memory controller includes: providing an input/output (I/O) circuit coupled to the flash memory device; and sending a data toggle set-feature signal to the flash memory device to enable, disable, or configure a data toggle operation of the flash memory device; the data toggle operation of the flash memory device is arranged to make the flash memory device control the flash memory device's data register selecting and transferring a first data unit and a second data unit to the flash memory device's I/O control circuit to make the I/O control circuit sequentially transmit the first data unit and the second data unit to the flash memory controller through the specific communication interface in response to a specific read command or a data toggle command transmitted by the flash memory controller.

Abstract: A flash memory device is disclosed. The memory cell array has a first plane and a second plane and stores a first data unit and a second data unit. The data register buffers the first data unit and the second data unit transmitted from the memory cell array when a read command or a data toggle command is received and stored by the command register. The control circuit performs a data toggle operation to control the data register selecting and transferring the first data unit and the second data unit to the I/O control circuit to make the I/O control circuit sequentially transmit the first data unit and the second data unit to the flash memory controller through a specific communication interface in response to the read command or the data toggle command. The transmission of the first data unit is followed by the transmission of the second data unit.

Abstract: The invention introduces a method for executing host input-output (IO) commands, performed by a processing unit of a device side, at least including: in response to different types of host IO commands, using multiple stages of a generic framework to drive a frontend interface to interact with a host side for transmitting user data read from a storage unit to the host side, and receiving user data to be programmed into the storage unit from the host side. The frontend interface includes a register, and a data line coupled to the host side. The stages of the generic framework are used to access to the register of the frontend interface and operate the data line of the frontend interface to complete interactions with the host side.

Abstract: A method of caching mapping table for use in a flash memory device having a flash memory controller and a flash memory is provided. The method includes: in response to a host read command, determining whether a group of a logical-to-physical (L2P) required by handling the host read command has been loaded to a DRAM of the flash memory controller; if the required group of the L2P mapping table has not been loaded to the DRAM, loading the required group of the L2P mapping table from the flash memory to a SRAM of the flash memory controller; directly accessing the SRAM to obtain an L2P address associated with the host read command from the required group of the L2P mapping table; and performing a read operation on the flash memory in response to the host read command according to the obtained L2P address.

Abstract: A method for performing data access control of a memory device with aid of a predetermined command and associated apparatus are provided. The method may include: utilizing the memory controller to receive a first single command from a host device through a transmission interface circuit of the memory controller; and in response to the first single command conforming to a predetermined format of the predetermined command, utilizing the memory controller to perform a series of operations according to the first single command, wherein the first single command represents a first duplicate command, for duplicating from a first source logical address to a first destination logical address. The series of operations may include: reading first data at the first source logical address; and writing the first data at the first destination logical address.

Abstract: The invention introduces an apparatus for detecting errors during data encryption. The apparatus includes a search circuitry and a substitution check circuitry. The key generation circuitry is arranged operably to convert a first value of one byte corresponding to a plaintext, an intermediate encryption result, or a round key into a second value of a K-bit according to an 8-to-K lookup table, where K is an integer ranging from 10 to 15 and the second value comprises (K minus 8) bits of a Hamming parity. The substitution check circuitry is arranged operably to employ check formulae corresponding to the 8-to-K lookup table to determine whether an error is occurred during a conversion of the first value of the one byte into the second value of the K-bit, and output an error signal when finding the error, where a total amount of the formulae is K minus 8.

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller performs a write operation in response to a write command, and during the write operation, the memory controller maintains a first quantity count value for counting a number of the predetermined memory block(s) that has/have been written with data, determine a number of the predetermined memory block(s) which is/are released in response to the write operation and maintains a second quantity count value based on this number. After the write operation, the memory controller performs a garbage collection and updates the first quantity count value based on the second quantity count value when determining that the host device has requested to perform a flush operation on the predetermined memory blocks.

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks which include one or more spare memory blocks not written with data and one or more predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller obtains a total number of remaining erasable count of the memory blocks and determines a setting value of a number of said one or more predetermined memory blocks according to a number of currently remaining spare memory block(s), a number of the predetermined memory block(s) that has/have been written with data among said one or more predetermined memory blocks, a predetermined threshold and the total number of remaining erasable count of the memory blocks, and configures the number of the predetermined memory block(s) as the buffer according to the setting value.