Abstract: A method of a storage device controller includes: using an interface circuit for receiving and storing different write address information of different write command signals sent from a host device, the different write address information being out of sequence; and, using multiple processor cores to rearrange the different write address information in sequence and then write data into at least one storage zone according to the different write address information rearranged in sequence.

Abstract: A method of a flash memory controller includes: controlling an I/O circuit using a set-feature signal, which carries a set-feature command, feature address, and parameter information, and transmitting the set-feature signal to a flash memory device; the feature address corresponds to a valid data portion or a dummy data portion following the valid data portion, and both the valid data portion and dummy data portion are comprised in a full page data which is to be written into a physical page unit of the flash memory device or to be read out from the physical page unit; the corresponding parameter information is used to record the valid data portion's column address and data length, the dummy data portion's column address and data length, the dummy data portion's column address and the valid data portion's, or the dummy data portion's data length and the valid data portion's data length.

Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information encoding and decoding are provided. The method may include: encoding internal information of the memory device and sending encoded result thereof to a host device, to allow the host device to store the encoded result in a memory within the host device as host-owned encoded device side table information at the host device; generating and storing multiple entries of address mapping control table into a RAM as at least one portion of device side table information at the memory device; decoding partial information of the host-owned encoded device side table information, performing checking operation on decoded result thereof, and selectively using the decoded result to determine physical address associated with logical address; and reading data from the NV memory according to the physical address.

Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information encoding and decoding are provided. The method may include: encoding internal information of the memory device and sending encoded result thereof to a host device, to allow the host device to store the encoded result in a memory within the host device as host-owned encoded device side table information at the host device; generating and storing multiple entries of address mapping control table into a RAM as at least one portion of device side table information at the memory device; decoding partial information of the host-owned encoded device side table information, performing checking operation on decoded result thereof, and selectively using the decoded result to determine physical address associated with logical address; and reading data from the NV memory according to the physical address.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: writing data into a plurality of pages of a specific block, and establishes or updates a F2H mapping table based on physical addresses of the plurality of pages and logical addresses of the data; using the F2H mapping table to update a H2F mapping table; initializing a flush-bitmap, wherein the flush-bitmap records a plurality of flush bits corresponding to the physical addresses of the plurality of pages, respectively; receiving a trim command from a host device, wherein the trim command asks to mark at least one of the logical addresses of the data as invalid; updating the H2F mapping data according to the trim command; updating the flush-bitmap according to the trim command; and writing the updated H2F mapping table and the updated flush-bitmap into the flash memory module.

Abstract: An explosion proof electronics enclosure (200), is provided having a first compartment (206) and a second compartment (207) defined by a body (205). A septum (208) is between the first compartment (206) and the second compartment (207). A first aperture (209) in the septum (208) connects the first compartment (206) and the second compartment (207). A cavity (225) communicates with the first aperture (209), wherein the cavity (225) comprises an undercut taper (226). A potting (230) in the cavity (225) conforms to the cavity (225) shape, and forms a substantially explosion-proof interface between the first compartment (206) and the second compartment (207).

Abstract: Methods and systems are provided for a coupling device. In one example, a system comprises a coupling device arranged between a gearbox and a motor, wherein the coupling device is further coupled to a vehicle frame.

Abstract: A data storage device includes a memory device and a memory controller. When a sub-region of the memory device is selected based on a predetermined rule to perform a data rearrangement procedure, the memory controller determines whether the selected sub-region is a system data sub-region. When determining that the selected sub-region is not a system data sub-region, the memory controller performs the data rearrangement procedure on the selected sub-region to move data corresponding to logical addresses belonging to the selected sub-region to a memory space of the memory device having continuous physical addresses, and when determining that the selected sub-region is a system data sub-region, the memory controller does not perform the data rearrangement procedure on the selected sub-region.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller uses a first predetermined memory block as a buffer to receive data from a host device. In response to a write command received from the host device, the memory controller determines a sub-region corresponding to the write command, determines whether the sub-region is a hot-write sub-region according to a write count corresponding to the sub-region and accordingly determines whether to use a second predetermined memory block as another buffer to receive data from the host device. When the memory controller determines that the sub-region corresponding to the write command is a hot-write sub-region, the memory controller writes the data into the second predetermined memory block. When the memory controller determines that the sub-region is not a hot-write sub-region, the memory controller writes the data into the first predetermined memory block.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller uses a first predetermined memory block as a buffer to receive data from a host device. In response to a write command received from the host device, the memory controller determines a sub-region corresponding to the write command, determines whether the sub-region is a system data sub-region and accordingly determines whether to use a second predetermined memory block as another buffer to receive data from the host device. When the memory controller determines that the sub-region corresponding to the write command is a system data sub-region, the memory controller writes the data into the second predetermined memory block. When the memory controller determines that the sub-region corresponding to the write command is not a system data sub-region, the memory controller writes the data into the first predetermined memory block.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller maintains a write count for each sub-region of the memory device. When the memory controller has selected one or more sub-regions to perform a data rearrangement procedure, the memory controller further determines whether a selected sub-region is a hot-write sub-region according to the write count corresponding to the selected sub-region. When the memory controller determines that the selected sub-region is not a hot-write sub-region, the memory controller performs the data rearrangement procedure on the selected sub-region to move data corresponding to logical addresses belonging to the selected sub-region to a memory space of the memory device having continuous physical addresses. When the memory controller determines that the selected sub-region is a hot-write sub-region, the memory controller does not perform the data rearrangement procedure on the selected sub-region.

Abstract: A wave energy capture system deployed in water converts mechanical motion induced by waves in the water to electrical energy. A controller of the wave energy capture system receives input regarding real-time wave conditions in a vicinity of the wave energy capture system. The controller applies a control model to the received input to select a value of a control parameter for the wave energy capture system, where the control model includes a model that has been trained using machine learning to take wave condition data as input and to output control parameter values selected based on the wave condition data in order to increase an amount of energy captured by the wave energy capture system. The controller implements the selected value of the control parameter on the wave energy capture system.

Abstract: A method for accessing a flash memory module includes: selecting a block in the flash memory module; selecting a specific encoding/decoding setting from a plurality of sets of encoding/decoding settings at least according to an erase count of the block, wherein the plurality of sets of encoding/decoding settings include different error correction code (ECC) lengths, respectively; utilizing the specific encoding/decoding setting to encode a data to generate an encoded data; and writing the encoded data into the block.

Abstract: A method for performing memory access of a Flash cell of a Flash memory includes: performing a series of sensing operations respectively corresponding to a plurality of sensing voltages, wherein a sensing voltage of a specific sensing operation of the series of sensing operations has a sensing voltage determined according to a result of an initial sensing operation of the series of sensing operations; determining a threshold voltage of the Flash cell according to at least a digital value generated by the series of sensing operations; and using the determined threshold voltage to perform soft decoding of the Flash cell.

Abstract: A method for accessing a flash memory module includes: determining a type of data to be written into the flash memory module; selecting a specific encoding/decoding setting from a plurality of sets of encoding/decoding settings at least according to the type of data, wherein the plurality of sets of encoding/decoding settings correspond to different data lengths, respectively; utilizing the specific encoding/decoding setting to encode the data to generate encoded data; and writing the encoded data into a block of the flash memory module.

Abstract: The invention relates to an apparatus and a system for debugging a solid-state disk (SSD) device. The apparatus includes a Joint Test Action Group (JTAG) add-on board; and a Raspberry Pi. The Raspberry Pi includes a General-Purpose Input/Output (GPIO) interface (I/F), coupled to the JTAG add-on board; and a processing unit, coupled to the GPIO I/F. The processing unit is arranged operably to: simulate to issue a plurality of JTAG command through the GPIO I/F to the SSD device for dumping data generated by the SSD device during operation from the SSD device.

Abstract: Provided herein is a driving apparatus for transporting a loaded object, which allows a drive-wheel to always be in contact with the ground even when the ground is uneven. The driving apparatus includes a loading plate (140, 240) on which a loaded object is loaded, a first support (110, 210) connected to a lower portion of one side of the loading plate (140, 240), a second support (120, 220) connected to a lower portion of the other side of the loading plate (140, 240), a hinge (130, 230) configured to connect the first support (110, 210) to the second support (120, 220) in a hinge structure, at least a pair of drive-wheels (160, 260) coupled to both sides of a lower portion of the second support (120, 220), and a driver configured to rotate and drive the drive-wheels (160, 260).

Abstract: A seating furniture chassis comprises a seat surface frame, a leg rest chassis, first and second struts, and a retractable and extendable leg rest extension. The leg rest chassis is pivotably arranged on the seat surface frame and pivotable from a folded-out position into a folded-in position. The first strut includes a first elongated hole and a first guide element. The second strut includes a second elongated hole and a second guide element, wherein the second guide element is arranged displaceably in the first elongated hole, and the first guide element is arranged displaceably in the second elongated hole. The leg rest extension is arranged on the leg rest chassis and connected thereto by the first and second struts.

Abstract: A flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller into a simplified command sequence so as to reduce the waiting time period of the command transmission and improve the performance of flash memory.

Abstract: Inertial Sensors and Inertial Measurement Units are provided. In one example, the inertial sensor comprises one or more microresonators, each microresonator supporting a corresponding optical resonance. The inertial sensor further comprises a micro-electro-mechanical inertial test mass suspended adjacent to and non-contiguous with the one or more microresonators, the test mass deflectable under the application of an inertial force. The inertial sensor further comprises one or more electrodes for counteracting a deflection of the test mass with an electrostatic force. The inertial sensor further comprises one or more optical couplers for coupling light into and out of a corresponding microresonator. The inertial sensor further comprises one or more detectors for detecting light received from the one or more microresonators by the one or more optical couplers.