Abstract: The present invention relates to a feedthrough (200) adapted for use within a passage (300). The feedthrough (300) has a body (202) having a first interface region (204) and a second interface region (206). The first interface region (204) comprises a platform region (214). At least one electrical conductor (212) extends through the body (202) and out of the body (202) to both the first interface region (204) and the second interface region (206). A printed circuit board (216) is attached to the platform region (214). At least one pin hole (234) defined by the printed circuit board (216) is configured to accept the at least one electrical conductor (212).

Abstract: A method for performing communications specification version control of a memory device in predetermined communications architecture with aid of compatibility management, associated apparatus and computer-readable medium are provided.

Abstract: A memory controller for use in a data storage device is provided. A low-density parity check (LDPC) process performed by the memory controller includes an initial phase, a decoding phase, and an output phase. The memory controller includes a variable-node circuit and a check-node circuit. During the initial phase, the variable-node circuit performs the following steps: obtaining a channel value, that is read from a flash memory, from a channel-value memory; transmitting the channel value to the check-node circuit to calculate a syndrome; and in response to the syndrome not being 0, setting a value of a register corresponding to each entry of a plurality of entries in a variable-node memory, and entering the decoding phase.

Abstract: A method for performing access management of a memory device with aid of serial number assignment timing control and associated apparatus are provided. The method includes: managing a plurality of spare blocks with a spare pool; popping a first block from the spare pool to be a host data block, and performing first subsequent operations, wherein the host data block is arranged to receive data from a host device, and serial number assignment of the host data block corresponds to a timing of fully programing the host data block; and popping a second block from the spare pool to be a garbage collection (GC) destination block, and performing second subsequent operations, wherein the GC destination block is arranged to receive data from a GC source block during a GC procedure, and serial number assignment of the GC destination block corresponds to a timing of starting using the GC destination block.

Abstract: A method, for calibrating signal processing devices in an interface circuit coupled to a host device, comprises: negotiating with the host device in a link up process about an operation mode for the interface circuit to operate in a calibration procedure; and calibrating a characteristic value of a first signal processing device and a characteristic value of a second signal processing device in the calibration procedure. The first signal processing device is disposed on a receiving signal processing path and configured to process a received signal and the second signal processing device is disposed on a transmitting signal processing path and configured to process a transmitting signal, and the interface circuit is configured to operate based on the operation mode in the calibration procedure.

Abstract: A method for performing automatic setting control of a memory device in predetermined communications architecture with aid of auxiliary setting management and associated apparatus are provided.

Abstract: A one-wheeled vehicle may comprise a board including first and second deck portions each configured to receive a left or right foot of a rider oriented generally perpendicular to a direction of travel of a board, and a pair of side rails, each of which are coupled to the first and second deck portions at distal ends. A top surface of each side rail defines a generally concave shape, such that a plane connecting distal edges of the end portions of the side rail is spaced apart from the central portion of the side rail. In some examples, a bottom surface of each side rail also defines a generally concave-upward shape. In some examples, a bottom surface of each side rail includes a central cutout.

Abstract: Fender assemblies are disclosed, each assembly including a frame and a fender. The frame has a first leg including a first coupling portion and a second leg including a first latch portion, and the frame is configured to be coupled to the vehicle with the first leg and the second leg on opposite sides of a wheel. The fender has a first end and a second end, the first end having a second coupling portion configured to releasably mate with the first coupling portion of the frame to form a manually releasable joint, the second end comprising a second latch portion configured to mate with the first latch portion of the frame to releasably secure the second end to the frame.

Abstract: A self-propelled, one-wheeled vehicle may include a board having two deck portions each having a concave front footpad configured to receive a foot of a rider, and a wheel assembly disposed between the deck portions. The concave front footpad has a rider detection sensor in the form of a membrane switch conforming to the shape of the footpad (e.g., facilitated by one or more slots formed in the membrane switch). A motor assembly drives the vehicle in response to board orientation and rider detection information.

Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

Abstract: A method for performing data fragmentation reduction control of a memory device in a predetermined communications architecture with aid of fragmentation information detection, associated apparatus and computer-readable medium are provided.

Abstract: A method for performing link management of a memory device in predetermined communications architecture with aid of handshaking phase transition control and associated apparatus are provided. The method may include: utilizing at least one upper layer controller of a transmission interface circuit to turn on a physical layer (PHY) circuit of the transmission interface circuit, for starting establishing a link between a host device and the memory device; before entering a first handshaking phase, utilizing the PHY circuit to receive any first incoming data sent from the host device to determine whether the any first incoming data indicates that the host device is in a corresponding first handshaking phase; and in response to the any first incoming data indicating that the host device is in the corresponding first handshaking phase, utilizing the PHY circuit to send first outgoing data that is equal to first predetermined data to the host device.

Abstract: A method of converting a directly measured mass flow rate to account for buoyancy is provided. The method includes directly measuring a mass flow rate of a material, measuring a density of the material, and using the measured density of the material to convert the directly measured mass flow rate into a mass value including a buoyancy of a fluid.

Abstract: Methods for operating a flowmeter diagnostic tool are provided that comprise interfacing the diagnostic tool with a flowmeter (5) sensor assembly (10). A base prover volume (BPV), a desired number of passes per run, and/or a maximum number of allowed runs may be input into the diagnostic tool. Flowmeter data is received. An estimated total prove time (TPT) necessary to pass a predetermined repeatability requirement, an estimated minimum number of runs needed to achieve the calculated TPT, and/or an estimated minimum BPV may be calculated.

Abstract: A method for performing data retention management of a memory device with aid of pre-shutdown control and associated apparatus are provided. The method may include: receiving a predetermined host command from a host device; in response to the predetermined host command, performing a re-programming procedure on the NV memory, for enhancing data storage reliability of the memory device, for example, reading stored data from at least one source location within the at least one NV memory element to prepare re-programming data according to the stored data, and programming the re-programming data into at least one destination location within the at least one NV memory element to be replacement of the stored data; and in response to the re-programming procedure being completed, sending completion information of the predetermined host command to the host device, to allow the host device to trigger the shutdown of the memory device.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for decoding a Low-Density Parity-Check (LDPC) code. The method, which is performed by a processing unit in an LDPC decoder, includes the following steps: determining whether a bit flipping algorithm when decoding a codeword enters a trapping state after an observation period during which a sequential selection strategy is used; and modifying a scheduling strategy to a non-sequential selection strategy and performing the bit flipping algorithm on the codeword under the non-sequential selection strategy when the bit flipping algorithm enters the trapping state. The codeword is divided into chunks in fixed-length and the sequential selection strategy indicates sequentially selecting the chunks in the codeword, so that the bit flipping algorithm is performed on one selected chunk only each time.

Abstract: A method for performing data management of a memory device with aid of targeted protection control and associated apparatus are provided. The method may include: receiving a first host command from a host device; sending a first operating command to a non-volatile (NV) memory to read first stored data from a first location within the NV memory; monitoring a read count of the first location to determine whether the read count of the first location reaches a read count threshold; monitoring at least one error bit count of other stored data of at least one other location within the NV memory to determine whether the at least one error bit count reaches an error bit count threshold; and starting a targeted protection procedure to process second stored data, for preventing the second stored data from being damaged by at least one reading behavior of the host device.

Abstract: A memory controller coupled to a memory device for accessing the memory device and includes a Universal Asynchronous Receiver/Transmitter (UART) and a microprocessor. The microprocessor is coupled to the UART and configured to control access operations of the memory device. The microprocessor is configured to perform an interrupt service routine in response to an interrupt. When performing the interrupt service routine, the microprocessor is configured to determine whether a predetermined signal has been received by a specific pin and when determining that the predetermined signal has been received by the specific pin, the microprocessor is configured to output a debug message through a transmitting terminal of the UART.

Abstract: A meter electronics (20) for determining a decay characteristic of a meter assembly (10) of a flow meter (5) is provided. The meter electronics (20) includes an interface (201) for receiving a vibrational response from a meter assembly (10), the vibrational response comprising a response to an excitation of the meter assembly (10) at a substantially resonant frequency, and a processing system (203) in communication with the interface (201). The processing system (203) is configured to receive the vibrational response from the interface (201), determine a response voltage (V) of the vibrational response, determine a decay characteristic (?) of the meter assembly (10) based on the response voltage (V), and compensate the decay characteristic (?) by using a previously determined decay characteristic-to-response voltage relationship.

Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.