Patents Assigned to Indian Institute of Science
  • Publication number: 20190120701
    Abstract: A nanocomposite has reduced Graphene oxide and silver nanoparticles. A method synthesizes a nanocomposite and fabricates a nanocomposite film on a substrate for sensor applications based on the principle of negative temperature coefficient (NTC) of piezoresistive temperature sensing elements.
    Type: Application
    Filed: April 7, 2017
    Publication date: April 25, 2019
    Applicant: INDIAN INSTITUTE OF SCIENCE
    Inventors: Nagarjuna NEELLA, Venkateswarlu GADDAM, Nayak Mangalore MANJUNATHA, Dinesh Narasimhiah SUBRAHMANYAM, Rajanna KONANDUR
  • Publication number: 20190085020
    Abstract: A multifunctional chemical agents comprising functional agents Fn1, Fn2 and linkers, for the linchpin directed (LDM), protein directed (PDPM) modifications of proteins, and Fn1 accelerated kinetic labeling by Fn2.
    Type: Application
    Filed: November 17, 2016
    Publication date: March 21, 2019
    Applicants: Department of Biotechnology, Indian Institute of Science Education and Research
    Inventors: Vishal RAI, Srinivasa Rao ADUSUMALLI
  • Patent number: 10211200
    Abstract: The present disclosure relates to a Silicon Controlled Rectifier (SCR) in non-planar technology to provide a robust ESD protection in System on Chip employing non-planar technologies. The disclosed SCR incorporates wire or fin shaped nanostructures extending from p-type tap to cathode, from the cathode to anode, and from the anode to n-type tap to provide parallel trigger paths to prevent problem of current crowding at the base emitter junction that limits efficient turn-on in conventional SCRs. The proposed structure helps in offering lower trigger and holding voltage, and therefore very high failure currents. The disclosed SCR has sub-3V trigger and holding voltage to provide an efficient and robust ESD protection in SOCs. The proposed device also offers three times better ESD robustness per unit area. Further the proposed SCR has no added capacitive loading and is compatible with standard process flow and design rules.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: February 19, 2019
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Mayank Shrivastava, Milova Paul, Christian Russ, Harald Gossner
  • Patent number: 10188136
    Abstract: The present invention discloses hydrophobin mimics of formula (I) comprising a protein head group, hydrophilic linker and hydrophobic tail and to a process for synthesis of library of hydrophobin mimics thereof. The hydrophobin mimics of the present invention self-assemble to form protein nanoparticles/nanocontainer either alone or in a specified chemical environment. The hydrophobin mimics (I) of the present invention find application in area of bio-nanotechnology.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: January 29, 2019
    Assignee: INDIAN INSTITUTE OF SCIENCE EDUCATION AND RESEARCH
    Inventors: Sandanaraj Selvaraj Britto, Mullapudi Mohan Reddy, Pavankumar Janardhan Bhandari, Kasuladevu Jagannadha Rao
  • Publication number: 20190013310
    Abstract: The present disclosure relates to a Dual Fin SCR device having two parallel fins on which cathode, anode, n- and p- type triggering taps are selectively doped, wherein one Fin (or group of parallel Fins) comprises anode and n-tap, and other Fin (or group of parallel Fins) comprises cathode and p-tap. As key regions of the proposed SCR (anode and cathode), which carry majority of current after triggering, are placed diagonally, they provide substantial benefit in terms of spreading current and dissipating heat. The proposed SCR ESD protection device helps obtain regenerative feedback between base—collector junctions of two back-to-back bipolar transistors, which enables the proposed SCR to shunt ESD current. The proposed SCR design enables lower trigger and holding voltage for efficient and robust ESD protection. The proposed SCR device/design helps offer a tunable trigger voltage and a holding voltage with highfailure threshold.
    Type: Application
    Filed: January 30, 2018
    Publication date: January 10, 2019
    Applicant: INDIAN INSTITUTE OF SCIENCE
    Inventors: Milova PAUL, Mayank SHRIVASTAVA, B. Sampath KUMAR, Christian RUSS, Harald GOSSNER
  • Publication number: 20190013781
    Abstract: The present disclosure relates to an integrated wideband Radio Frequency (RF) amplifier, based on a complementary metal oxide semiconductor (CMOS) technology. In an embodiment the amplifier addresses the shortcomings of conventional wideband amplifiers and is based on a distributed amplifier (DA) topology which typically exhibit severe performance degradation when externally loaded with parasitic circuit elements. In an embodiment of the present invention a buffer amplifier at the output of a conventional DA is able to compensate the impact of parasitic elements. The disclosed circuit can be implemented by fabricating the wideband RF amplifier integrated circuit (IC) on a 130 nm CMOS technology or other comparable CMOS technologies.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 10, 2019
    Applicant: Indian Institute of Science
    Inventors: Gaurab BANERJEE, Arnab CHAKRABORTY, Jaideep CHAUHAN
  • Publication number: 20180354066
    Abstract: The present invention relates to nanoprocessing and heterostructuring of silk. It has been shown that few-cycle femtosecond pulses are ideal for controlled nanoprocessing and heterostructuring of silk in air. Two qualitatively different responses, ablation and bulging, were observed for high and low laser fluence, respectively. Using this approach, new classes of silk-based functional topological microstructures and heterostructures which can be optically propelled in air as well as on fluids remotely with good control have been fabricated.
    Type: Application
    Filed: August 14, 2018
    Publication date: December 13, 2018
    Applicant: INDIAN INSTITUTE OF SCIENCE EDUCATION AND RESEARCH
    Inventors: Kamal Priya SINGH, Mehra Singh Sidhu, Bhupesh Kumar
  • Patent number: 10131922
    Abstract: The invention is for an increased isoprenoid production by carotenoid optimization in an expression system and the carotegenic gene for optimization may be geranylgeranyl diphosphate synthase (GGPPS), phytoene synthase (PSY1), conserved CRTI or mutated CRT1A393T, BT1 of S. cerevisae. The carotogenic gene from red yeast which includes Rhodosporidium spp. Rhodotorula spp, Sporidiobolus spp., Leucosporidium spp., Sporobolomyes spp. is selected.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: November 20, 2018
    Assignee: Indian Institute of Science Education and Research
    Inventors: Manisha Wadhwa, Anand Kumar Bachhawat
  • Publication number: 20180226317
    Abstract: The present disclosure relates to a thermal management solution for ESD protection devices in advanced Fin- and/or Nanowire-based technology nodes, by employing localized nano heat sinks, which enable heat transport from local hot spots to surface of chip, which allows significant reduction in peak temperature for a given ESD current. In an aspect, the proposed semiconductor device can include at least one fin having a source and a drain disposed over a p-well or a n-well in a substrate; an electrically floating dummy metal gate disposed close to drain or hot spot over at least a portion of the at least one fin, and an electrical metal gate is disposed close to the source; and a nano-heat sink operatively coupled with the dummy metal gate and terminating at the surface of chip in which the semiconductor device is configured so as to enable transfer of heat received from the at least one fin through the dummy metal gate to the surface of the chip.
    Type: Application
    Filed: January 30, 2018
    Publication date: August 9, 2018
    Applicant: INDIAN INSTITUTE OF SCIENCE
    Inventors: Mayank SHRIVASTAVA, Milova PAUL, Christian RUSS, Harald GOSSNER
  • Publication number: 20180219007
    Abstract: The present disclosure relates to a Silicon Controlled Rectifier (SCR) in non-planar technology to provide a robust ESD protection in System on Chip employing non-planar technologies. The disclosed SCR incorporates wire or fin shaped nanostructures extending from p-type tap to cathode, from the cathode to anode, and from the anode to n-type tap to provide parallel trigger paths to prevent problem of current crowding at the base emitter junction that limits efficient turn-on in conventional SCRs. The proposed structure helps in offering lower trigger and holding voltage, and therefore very high failure currents. The disclosed SCR has sub-3V trigger and holding voltage to provide an efficient and robust ESD protection in SOCs. The proposed device also offers three times better ESD robustness per unit area. Further the proposed SCR has no added capacitive loading and is compatible with standard process flow and design rules.
    Type: Application
    Filed: January 30, 2018
    Publication date: August 2, 2018
    Applicant: INDIAN INSTITUTE OF SCIENCE
    Inventors: Mayank SHRIVASTAVA, Milova PAUL, Christian RUSS, Harald GOSSNER
  • Publication number: 20180215709
    Abstract: The present invention relates to compounds that inhibit the activity of Type III deiodinase (DIO3). The present invention further relates to methods for treating or preventing depression, depression associated with other psychiatric or general medical diseases or conditions, condition amenable to treatment with known anti-depressants and cancer, particularly by using the compounds of the invention.
    Type: Application
    Filed: March 16, 2015
    Publication date: August 2, 2018
    Applicants: HADASIT MEDICAL RESEARCH SERVICES AND DEVELOPMENT LTD., INDIAN INSTITUTE OF SCIENCE
    Inventors: Bernard LERER, Mugesh GOVINDASAMY, Tzuri LIFSCHYTZ
  • Patent number: 10026441
    Abstract: The present disclosure relates to a method and apparatus for processing of multi-dimensional readback signal from magnetic recording or optical, physical data recording so as to reduce/control Inter Symbol Interference (ISI) and noise within acceptable limits. The method is based on Partial Response Maximum Likelihood (PRML) detection and takes care of time varying channel conditions. In an embodiment, the filter coefficients of both the equalizer and the partial response (PR) target are jointly adapted to account for the channel condition for both separable and non-separable targets thus reducing signal detection complexity. In an aspect, the disclosure provides an apparatus that incorporates an adaptation engine along with the equalizer and the PR target that updates filter coefficients of both the equalizer and the PR target following the formulated mathematical equations.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: July 17, 2018
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Shayan Srinivasa Garani, Chaitanya Kumar Matcha, Arnab Dey
  • Patent number: 10024799
    Abstract: The invention provides a method for chemical signature resolved detection of a concealed object within a system. The method includes irradiating the system at a plurality of positions with aplurality of electromagnetic radiation of specific wavelength; capturing a certain component of the scattered electromagnetic radiation from the object at a plurality of locations along various 3D planes around the system; obtaining a plurality of profiles from the captured component of the scattered electromagnetic radiation; filtering the profiles to obtain a chemical signature specific to the object; and resolving the chemical signatures to detect the concealed object, wherein, the step of detection includes determination of the shape, size and location of the object.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: July 17, 2018
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Siva Umapathy, Sanchita Sil, Gagan Dhal, Freek Ariese
  • Publication number: 20180159418
    Abstract: The present invention is in relation to a synchronous buck converter comprising gate driver circuit, incorporated with passive elements for conversion of unipolar voltage produced by a standard gate driver to a bipolar voltage along with bootstrap technique to drive the normally on metal oxide semiconductor field effect transistor.
    Type: Application
    Filed: August 4, 2017
    Publication date: June 7, 2018
    Applicant: INDIAN INSTITUTE OF SCIENCE
    Inventors: Kaushik BASU, Sanket PARASHAR
  • Patent number: 9983136
    Abstract: The invention provides a method for obtaining sample specific signatures. The method comprises of irradiating the sample at a predefined location with an electromagnetic radiation of specific wavelength; selectively capturing a certain component of the scattered electromagnetic radiation to obtain a plurality of profiles; and filtering the profiles to obtain a sample specific signature. The invention provides an apparatus for obtaining sample specific signatures.
    Type: Grant
    Filed: September 2, 2013
    Date of Patent: May 29, 2018
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Siva Umapathy, Sanchita Sil, John Kiran
  • Patent number: 9969696
    Abstract: The present disclosure relates to compound of structural “formula I” and a method for preparing a compound of structural formula I. The disclosure further relates to a method of arresting DNA double-strand break (DSB) repair by employing the compound of structural formula I.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: May 15, 2018
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Sathees Chukkurumbal Raghavan, Mrinal Srivastava, Subhas Somalingappa Karki, Bibha Choudhary
  • Publication number: 20180109188
    Abstract: The present invention provides a hybrid combination of GaN transistor and Si transistor that are connected in an unique manner in a synchronous DC-DC power converter. The GaN transistor acts as active switch and the Si transistor acts as synchronous diode to reduce the power loss in a DC-DC power converter.
    Type: Application
    Filed: August 4, 2017
    Publication date: April 19, 2018
    Applicant: INDIAN INSTITUTE OF SCIENCE
    Inventors: Mohammad Hassan HEDAYATI, Vinod JOHN
  • Patent number: 9816159
    Abstract: The present subject matter describes Ni—Al—Zr alloys, which include Ni as the major component, with the additions of 9-20% Al and 4-14% Zr by atomic percentage. In one embodiment, the present subject matter describes a group of alloy compositions in a Nickel-Aluminum-Zirconium (Ni—Al—Zr) system corresponding to a concentration range of about 9-20% Al and about 4-14% Zr by atomic percentages, and the balance being Ni. In other embodiment, the present subject matter includes at least one eutectic constituent including at least two of the intermetallic compounds or phases Ni3Al, NiAl, Ni5Zr, Ni7Zr2 and derivatives that are realized within the aforementioned composition group.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: November 14, 2017
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Chandrasekhar Tiwary, Sanjay Kashyap, Olu Emmanuel Femi, Dipankar Banerjee, Kamanio Chattopadhyay
  • Patent number: 9749716
    Abstract: Sensors within sensor node networks may communicate bio-event or other types of measurement results/decisions between each other using signal transmission variations. Each sensor node within a network and between networks may transmit and receive signals. A sensor node may scale a signal transmission power in a manner that is proportional to a confidence level of a decision or measurement about an event being detected. Each sensor node will receive transmissions from neighboring nodes, and can refine an estimate about an occurrence of the event at its location based on received signal strengths, for example.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: August 29, 2017
    Assignee: INDIAN INSTITUTE OF SCIENCE (IISC)
    Inventor: Neelesh B. Mehta
  • Patent number: 9741656
    Abstract: The present invention provides a high-frequency integrated device, comprising a substrate including at least an on-chip active and passive member and a ferrite layer bonded to the substrate through an interfacial bridge and substantially wrapping plurality of surfaces of said at least on-chip active and passive members. The present invention also provides a system incorporating the high-frequency integrated device of the present invention. The present invention further provides a process for the preparation of the high-frequency integrated device.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: August 22, 2017
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Ranajit Sai, Srinivasarao Ajjampur Shivshankar, Navakanta Bhat, Vinoy Kalarickaparambil Joseph