Abstract: In order to shorten the transient recovery duration, the phase-locked loop has a voltage-controlled oscillator providing an oscillator signal to a first frequency divider. The first frequency divider divides the frequency of the oscillator signal, generates a first divider output signal therefrom, and passes it to a phase comparator during the transient recovery duration of the phase-locked loop. Furthermore, a unit is provided, which, after the transient recovery duration of the phase-looped loop, divides the frequency of the first divider output signal and passes it to the phase comparator. The phase comparator compares the first divider output signal with a first reference signal during the transient recovery duration. The phase comparator compares the divided divider output signal with a second reference signal after the transient recovery duration. The output of the phase comparator is connected to the voltage-controlled oscillator via a controllable charge pump.

Abstract: An analog-to-digital converter circuit including an analog-to-digital converter and calibrating circuit, preferably in the form of a digital logic, for the auto-calibration of the analog-to-digital converter. This configuration produces a very high quality analog-to-digital converter with a very low surface area requirement. The calibrating circuit corrects any errors of the analog-to-digital converter outside or inside of the analog-to-digital converter.

Abstract: A method of manufacturing a metal-insulator-metal capacitor (MIMCap) (36) including first conductive lines (15), capacitor dielectric (26) and second conductive lines (28), the MIMCap (36) including horizontal capacitive portions (32) and vertical capacitive portions (34). The method includes forming first conductive lines (15) in a first insulating layer (14) of a wafer (10), depositing a second insulating layer (22), depositing a resist, removing portions of the resist, removing exposed portions of the second insulating layer (22) and portions of the first insulating layer (14), removing the remaining resist, and then depositing a capacitor dielectric (26) and second conductive lines (28).

Abstract: A frequency compensation circuit includes a first and a second compensation capacitor for a frequency-compensated amplifier to which a chopped useful signal can be supplied. In a first clock phase, the useful signal is respectively supplied to the first compensation capacitor, and in a second clock phase the useful signal is respectively supplied to the second compensation capacitor. As a result, a stable, frequency-compensated amplifier is specified in which charge reversal in the frequency compensation capacitors or Miller capacitors is avoided, making possible a configuration with a small chip area. The principle is suited particularly to Hall sensors operated in chopped mode.

Abstract: A variable gain amplifier (“VGA”) having an open loop architecture is disclosed. The VGA includes one or more gain cells coupled in the signal path to amplify a given input signal. The VGA further includes a replica gain cell having a gain servo circuit which amplifies a gain reference signal according to a programmable gain input and equalizes the amplified reference signal to the original unamplified reference signal, continuously generating a gain control input to the signal path gain cells based on the equalization. This gain control input reflects the gain set by the programmable gain input as adjusted for process, temperature and supply voltage variations. The replica gain cell further includes a common mode voltage servo circuit which senses the common mode voltage of the amplified reference signal and equalizes it to a common mode voltage reference, generating a common mode voltage control signal to the signal path gain cells to regulate their common mode voltage.

Abstract: A timing device for generating and outputting a plurality of signal edges by changing signal statuses at predeterminable times. The timing device includes a cyclically addressable memory in which a plurality of time events are stored. Each time event is assigned a time value, which corresponds to a predetermined time, and a plurality of predetermined signal statuses. The timing device further includes a comparator, which compares the current count of a counter to the time value of a time event, which has just been acquired from memory. Given a match, the next time event is read from the memory. The timing device also includes an output device which outputs the predetermined signal statuses. With the timing device it is possible to freely program periodically recurring time indications by allocating memory accordingly.

Abstract: A method of manufacturing a vertical DRAM device (10) having isolation trenches (38) with a controlled height. A support liner (54) is disposed over support regions (18) of a wafer. A first insulating layer is disposed over the wafer, and the first insulating layer is removed from a top surface of the wafer, leaving a portion (52) of the first insulating layer disposed over at least the array region (16). The isolation trenches (38) may be recessed below a top surface of the wafer pad nitride (14), so that portions of the first insulating layer (52) are left remaining over the support liner (54) over the support region isolation trenches (38).

Abstract: Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.

Abstract: A voltage-controlled oscillator for frequency modulation includes an oscillator core with a tunable resonant circuit component which is driven with a control voltage. Furthermore, a modulator component is provided which is driven with a modulation signal for frequency modulation. The modulator component is additionally coupled to the terminal for supplying the control voltage. As a result, a constant modulation deviation can be achieved over the entire tuning range even in the case of oscillators having a large tuning range. The oscillator circuit is particularly suitable for use in transmitting circuits for digital communication.

Abstract: The photomask and the associated method of lithography and mask technique enable production of a regular configuration of resist dots or holes. At least one photomask is a phase mask. The method is useful for the production of magnetic memory components, in particular MRAM memories, having elliptically shaped magnetic memory elements of high density.

Abstract: A semiconductor Dynamic Random Access Memory (DRAM) cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A Shallow Trench Isolation (STI) region is used as a masking region to confine the channel region of the access transistor, the first and second output regions of the access transistor, and a strap region connecting the second output region to the storage capacitor, to a narrow portion of the trench. The so confined second output region of the access transistor has reduced leakage to similar second output regions of adjacent memory cells. Adjacent memory cells can then be placed closer to one another without an increase in leakage and cross-talk between adjacent memory cells.

Abstract: Semiconductor chips are mounted on a multilayer wiring of a silicon carrier substrate, while the bottom side of the carrier substrate is provided with soldering contacts in the form of solder balls and is structured in such a way that for each soldering contact a cavity, which extends through the silicon carrier substrate and is filled by the respective solder ball, is formed, so that the solder ball itself makes contact with the multilayer wiring. In this configuration, at least the side walls of the cavity are lined with an insulating material. The insulating layer is applied prior to the application of the multilayer wiring to the structured silicon carrier substrate.

Abstract: A method for improving acoustic sidetone suppression in hands-free telephones, in particular for use in motor vehicles, is described. The telephone has a level discriminator and a plurality of adaptive echo compensation filters each processing a subband. In at least one subband, a further adaptive filter (a shadow filter) of a lower order is connected in parallel with the adaptive echo compensation filter. Spatial changes are detected with the aid of a combined evaluation of a correlation analysis and a residual error comparison of the two competing, adaptive filters.

Abstract: An EPROM-like memory includes a substrate having a source region, a drain region, and a channel. The memory includes a gate stack formed by a gate oxide, a storage electrode, a second gate oxide and a gate electrode. The gate oxide is configured on the substrate above the channel. The storage electrode is configured on the gate oxide. The second gate oxide is configured on the storage electrode. The gate electrode is configured on the second gate oxide. The memory includes an interspace that is configured between the drain region and the storage electrode. The interspace is filled with a gas or contains a vacuum. The memory includes an outer spacing web that is configured laterally beside the gate stack. The outer spacing web is also configured on the drain region. The outer spacing web is made of doped polycrystalline silicon.

Abstract: An antifuse having a dielectric disposed between a plurality of conductive elements is programmed with one of the conductive elements connected to a capacitor. The antifuse is programmed to an “on” state by precharging the capacitor and then applying a programming voltage to another one of the conductive elements. This results in the breakdown of the interposed dielectric to form a conductive link between the conductive elements. Immediately, following the formation of a conductive link, the electrical energy stored in the capacitor is released through the conductive link across the dielectric. Further, the capacitor can be common to a plurality of programmable antifuses and the application of the programming voltage serves to select one of the plurality of antifuses to be ‘blown’. This arrangement can be realized in a FET and the device can be easily integrated in the CMOS process commonly used for the manufacture of memory arrays and logic circuitry.

Abstract: Test circuit for testing a circuit to be tested, having a test data generator, which generates test data in a manner dependent on data control signals which are received via data control lines from an external test unit, a data output driver for outputting the generated test data via data line pairs of a differential data bus to the circuit to be tested, a data input circuit for receiving data that are read from the circuit to be tested and transmitted via the data line pairs of the differential data bus, a data comparison circuit, which compares the generated data and the read-out data and, in a manner depend at on the comparison result transmits an indication signal, which indicates whether the circuit to be tested is functional, to the external test unit via an indication signal line.

Abstract: A method of monitoring and/or controlling machining plans having time-dependent machining parameters includes measuring desired time-dependent machining parameters as a measured curve, generating time-independent numerical values from the measured machining parameters, and entering the time-independent numerical values into a classifier distinguishing between normal states of the machining plant and abnormal states of the machining plant. Training vectors regarded as abnormal can be filtered out from training vectors available by determining a distance of each training vector from every other training vector with a selected measure of distance for filtering of the abnormal training vectors, the training vectors having components made of time-independent numerical values, and the classifier can be trained with training vectors.

Abstract: An electronic circuit in an integrated circuit having memory cells is described. The circuit permits information to be written to particular memory cells only once, so that subsequent writing to the particular memory cells is blocked. The circuit is used in a test structure for integrated circuits on a wafer. A method for testing integrated circuits on a wafer that are connected to a test apparatus is also described. Once the supply voltage to a first circuit to be tested has been turned on, a preliminary test is carried out to ascertain parameters that need to be set. The supply voltage is then applied to a next circuit to be tested, a preliminary test is carried out, and memory cells have information written to them, until the parameters have been set for all the connected circuits to be tested. The test apparatus then carries out the actual operational test in parallel for all the connected circuits to be tested.

Abstract: A configuration for producing test signals for testing semiconductor chips includes a clock signal source for producing a clock signal, and a tester. The test signals are produced on the respective semiconductor chips in a precise temporal sequence with respect to the clock signal. The temporal sequence of the test signals on a respective one of the semiconductor chips is determined from the clock signal. Latches are connected downstream of each of the signal inputs for each of the test signals. A DLL unit uses the clock signal to produce a delayed clock signal to activate the latches. Switches to be driven by a test mode signal are disposed in parallel with the latches. A method for producing test signals for testing semiconductor chips includes the steps of supplying test signals to semiconductor chips in a precise temporal sequence with respect to a clock signal, and determining from the clock signal the temporal sequence of the test signals on each of the semiconductor chips.

Abstract: A semiconductor configuration includes a semiconductor body with a first connection zone of a first conductivity type, a second connection zone of the first conductivity type, a channel zone of the first conductivity type, and at least one control electrode surrounded by an insulation layer. The channel zone is formed between the first connection zone and the second connection zone. The at least one control electrode extends, adjacent to the channel zone, from the first connection zone to the second connection zone. The first connection zone, the second connection zone and the at least one control electrode extend in the vertical direction such that, when a voltage is applied between the first and second connection zones, a current path along the lateral direction is formed in the channel zone.