Abstract: A circuit configuration for measuring or calibrating current of components in memory elements, preferably, EPROM or EEPROM memory elements, includes a memory cell field, a reference cell field, a current comparator, a digital-analog converter receiving a digital signal having digital values and outputting predetermined current values based upon receiving corresponding ones of the digital values, a first switch having an output connected to a first input of the current comparator, a first input connected to the memory cell field, and a second input connected to the reference cell field, and a second switch having an output connected to a second input of the current comparator, a first input connected to the reference cell field, and a second input connected to the digital-analog converter. The second switch can have a third input to be connected to an external current source.

Abstract: A trench capacitor for use in a semiconductor memory cell is formed in a substrate. The trench capacitor includes a trench having an upper region and a lower region, an insulation collar formed in the upper region on a trench wall of the trench, and a buried well, through which the lower region of the trench at least partly extends. The trench capacitor further includes, as an outer capacitor electrode, a conductive layer lining the lower region of the trench and the insulation collar, a dielectric layer lining the conductive layer, and a conductive trench filling which is filled into the trench as an inner capacitor electrode. A method of fabricating a trench capacitor is also provided.

Abstract: A circuit configuration for performing a selective changeover of word lines of a memory matrix between an activation potential and a deactivation potential uses selectively addressable drivers. The changeover of a word line input terminal from the activation potential to the deactivation potential is effected through the relevant driver if a deactivation signal is brought to an active state by a timing control circuit. In order to accelerate the deactivation of the word lines, a respectively assigned deactivation auxiliary switch is connected to each of the word lines at at least one terminal remote from the input terminal. The deactivation auxiliary switch is controlled by a timing control circuit such that it connects the remote terminal to the deactivation potential practically at the same instant at which the assigned driver changes the input terminal of the relevant word line from the activation potential over to the deactivation potential.

Abstract: An edge termination is produced that is capable of handling high voltages. The edge termination is produced in a base material wafer that is produced in accordance with the principle of lateral charge compensation. The edge termination is formed in the base material wafer by implanting a rapidly diffusing dopant. Preferred dopants are selenium and sulfur. The high-voltage withstand strength is effected by a resulting doping profile which increases towards the edge termination.

Abstract: In accordance with the present invention, a method for employing and removing inorganic anti-reflection coatings, includes the steps of providing a first dielectric layer on a semiconductor device structure to be processed, the first dielectric layer being selectively removable relative to the semiconductor device structure, and forming an inorganic dielectric anti-reflection coating (DARC) on the first dielectric layer, the DARC being selectively removable relative to the first dielectric layer. A resist layer is patterned on the DARC. The resist is selectively removable relative to the DARC. The semiconductor device structure is etched, and the resist layer, the DARC and the first dielectric layer are selectively removed.

Abstract: An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the resistance of buried bit lines. The layer or layer sequence has been patterned in strip form so as to correspond to the bit lines and is arranged on the source/drain regions of memory transistors having an ONO memory layer sequence and gate electrodes that are arranged in trenches. The metal silicide is preferably cobalt silicide, and the metal-containing layer is preferably tungsten silicide or WN/W. .

Abstract: A method for generating a signal pulse sequence with a predetermined stable fundamental frequency from a sequence of signal pulses whose frequency fluctuates and has the spectral components whose frequency is at least a predetermined multiple of the fundamental frequency. The method includes, feeding the sequence of signal pulses to a digital filter, arranging a passband of the digital filter around the fundamental frequency, blocking, using the digital filter, around a predetermined half the sampling frequency. The method further includes outputting a signed output signal when the digital filter is excited, and generating a clock signal pulse for each change in sign of the output signal.

Abstract: A circuit for generating a temperature-stabilized reference voltage uses the current-mode technique, in which two partial currents are superimposed on each other and converted into the reference voltage. One partial current is generated by an asymmetric differential amplifier with two lateral bipolar transistors of different area. In order to generate the other partial current, an electrical resistor is disposed between the common node of the differential amplifier and ground.

Abstract: The object is to discharge a first capacitor from a high voltage to a low voltage. To this end, the one electrode of the first capacitor is linked with the one electrode of a second capacitor via a FET path. The other two electrodes of the two capacitors are connected to reference potential. A voltage source with its internal resistance is connected in parallel to the second capacitor. A discharge path leads from the one electrode of the first capacitor from the paths of two FET and a protective resistor to the reference potential. A current path leads from the one electrode of the second capacitor to the reference potential via the paths of two additional FET. A control unit switches on the discharge path. Once the voltage of the first capacity has decreased to the required lower value, the discharge path is blocked while a holding path is opened.

Abstract: Methods and reticles for evaluating lenses are disclosed. In one instance, a reticle which permits light to pass therethrough is provided which includes a first surface with a grating profile formed thereon. The grating profile includes a plurality of grouped stepped portions. Each group of the stepped portions includes a first step which prevents light from propagating therethrough, a second step which propagates light therethrough and a third step which propagates light therethrough at an angle 60 degrees out of phase with the light propagated through the second step.

Abstract: An alternating phase shift mask (400) and method of manufacturing thereof including assist edges (450) and (452) surrounding a main phase edge (420). Assist edges (450) and (452) improve the resolution of the alternating phase shift mask (400), thus enabling the patterning of smaller size features on a semiconductor wafer.

Abstract: Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such semiconductor devices.

Abstract: A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of bon axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the <100> crystallographic plane and another one of such planes being the <1 10> plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the with substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the <110> plane being oxidized at a higher rate than sidewalls in the <100> plane producing silicon dioxide on the silicon nitride layer having thickness over the <110> plane greater than over the <100> plane.

Abstract: A coupling system includes an optical plug-in connector, a coupling partner and a retaining element. The housing of the plug-in connector is provided with a sliding key and with two springy detent limbs which include a detent nose for engaging with the coupling partner. In order to receive the plug-in connector, the coupling partner is provided with a plug inlet which has recesses that correspond to the detent noses of the plug-in connector. A retaining element includes a laterally displaceable outer housing and an inner housing that is pivotally arranged therein. A locking element is provided as a two-limb lever that is arranged on the inner housing and that serves to lock the plug-in connector in the retaining element. When inserting the plug inlet, this locking is released once the plug-in connector and plug inlet are engaged with one another.

Abstract: An oscillator circuit is described and has an oscillator core with at least one inductance and, connected thereto, a first and second capacitance. A deattenuator is coupled to the oscillator core and has two transistors, which are cross-coupled to one another in a non-direct-electrical coupling. The respective load terminal of a respective transistor is directly connected to a reference-ground potential terminal. The non-direct-electrical, for example inductive, coupling of the transistors in combination with the transistors directly connected to ground enables a greater modulation capability and also a smaller phase noise of the oscillator circuit. In this case, the transistors are operated as current switches. In preferred embodiments, the oscillator circuit has a regulating circuit for a bias voltage and an operating-current setting.

Abstract: A field-effect-controllable semiconductor component and a method for fabricating an electrode of the component includes a semiconductor body having a first zone of a first conduction type, a second zone of a second conduction type disposed above the first zone, and at least one trench extending into the semiconductor body in a vertical direction through the second zone, applying a first insulation layer at least in a region of the second zone in the trench, applying a first layer of electrode material to the semiconductor body, applying an intermediate layer to the first layer, applying a second layer of electrode material to the intermediate layer, removing a portion of the second layer and of the intermediate layer to leave the intermediate layer and the second layer at least partly in the trench, and patterning the first layer.

Abstract: A memory cell configuration includes a magnetoresistive element with an annular cross-section in a layer plane, a first line and a second line. The first and second lines crossing each other. The magnetoresistive element is disposed in the crossing region between the first line and the second line. The first line and/or the second line include at least one first portion, in which the predominant current component is oriented parallel to the layer plane, and one second portion, in which the predominant current component is oriented perpendicular to the layer plane.

Abstract: Support matrices for semiconductors are often disposed with spacers on the semiconductor chip. The spacers are composed of silicone that flows into the region of the bonding leads and prevents reliable electrical connection of the bonding leads to the semiconductor chip. In order to prevent the flow, the support matrix for integrated semiconductors has a frame, conductor track structures and at least one bonding lead for connecting the conductor track structures to the integrated semiconductor. The bonding lead has, between a bonding region and the conductor track structures, at least one barrier for preventing the flow of flowable material onto the bonding region. A method for producing such support matrices is likewise described.

Abstract: A method for producing a holding configuration for at least one sheathed optical fiber conductor, which includes forming a holding body with a through-channel having a first channel section expanded over an expansion region into a second channel section opening into an outlet opening having a rounded rim.

Abstract: With the aid of the method for fault analysis according to the invention, a wide variety of chips are mapped by means of a transformation onto at least one uniform comparable wafer map. This transformation or resealing enables a chip-area-independent assessment of the products or the fabrication processes. The method for fault analysis according to the invention furthermore has the advantage that the information thus obtained can be stored very compactly in corresponding wafer databases and is thus available for further evaluations.