Abstract: A method for producing circuit structures on a semiconductor substrate is described. Photoresist structures are formed, which define functional circuit structures and dummy circuit structures, whereby the dummy circuit structures which are smaller than a minimum structural size are joined to an additional second dummy circuit structure. The additional circuit structure is provided in such a way that the minimum structural size, which is determined by a smallest required joint surface of the photoresist on the substrate, is exceeded. A semiconductor circuit is also provided, which includes functional circuit structures and dummy circuit structures, the dummy circuit structures being joined to the additional dummy circuit structures.

Abstract: In a receiving method for mobile radio applications, a given user data signal and at least one further user data signal located within the same frequency band are received. These two user data signals are equalized with an adaptive multiuser data detector and with a multiuser channel decoder that is connected in the feeback path to the adaptive muliuser data detector. Noise-reduction in the given user data signal is achieved by taking into consideration, during channel decoding, an extrinsic information item generated during source decoding.

Abstract: The invention concerns a voltage-current converter having: a first current mirror containing two transistors that are designed such that under identical drive conditions the current flowing through the first transistor is greater than the current flowing through the second transistor by a predetermined factor. The current through the second transistor constitutes the output current of the voltage-current converter. The very large area required in integrated circuits for known voltage-current converters is reduced by providing a second current mirror containing two transistors. The two current mirrors are connected in series to a supply voltage. A MOSFET is connected in series with the first transistor of the first current mirror. The gate of the MOSFET is connected to the input voltage.

Abstract: A method for driving a switch in a switched-mode power supply, in which the switch is connected in series with a primary coil of a transformer and in which a control signal dependent on an output voltage is available. In this case, reference instants at which a voltage present across the switch corresponds to a first reference voltage value or at which a voltage present across the primary coil corresponds to a second reference voltage value are detected and counted, the switch being closed again only after the number of detected reference instants has reached a comparison numerical value. The invention furthermore relates to a switched-mode power supply for realizing the method according to the invention.

Abstract: A delay locked loop has a filter in order to set the delay time of a delay path in a manner dependent on the phase difference of input and output clock signals. The phase difference is ascertained by a phase detector. An additional control circuit determines the number of drive pulses of the filter and additionally controls the number of effective counter stages of a counter that forms the filter. The transient recovery time of the delay locked loop is thereby reduced.

Abstract: Integrated semiconductor circuits have MOS transistors whose gate electrodes are provided with dopings in order to set the electrical potential of the channel area by changing the ionization energy (work function) of the electrons. Transistors in semiconductor circuits, which have both a memory area and a logic area, are produced either using different dopings for pMOS and NMOS transistors in the logic area (dual work function) or using common source/drain electrodes in the memory area (borderless contact), with all the transistors in the semiconductor circuit receiving the same gate doping in the latter case. A method is proposed by which a dual work function and a borderless contact can be produced at the same time. Furthermore, the method results without any additional effort in a trench between the gate layer stacks of the memory area and of the logic area, which prevents lateral ion diffusion.

Abstract: An electronic driver circuit for directly modulated semiconductor lasers is described. The drive circuit has a first circuit for generating a constant current and a second circuit for modulating the constant current. The second circuit generates, as a function of a digital data signal, a modulation current that is superimposed on the constant current, the modulated current being fed to a semiconductor laser. According to the invention, a third circuit is additionally provided which keeps the driver circuit at a low impedance during a rising edge and/or a falling edge of the current through the semiconductor laser. As a result, the signal shape of the optical output signals of the semiconductor laser can be improved, and the driver circuit can be operated at higher data rates, in particular at data rates of up to 12 Gbit/s.

Abstract: After an SBT layer is precipitated onto a substrate, the SBT layer is structured as a still amorphous layer. Only subsequently is it subjected to a crystallization process. Layers produced in this manner have a relatively high degree of dielectric strength and have no stoichiometric deviations on the etched edges.

Abstract: Memory cells each include one transistor and one capacitor. A memory node of the capacitor is disposed in a first indentation, while a gate electrode of the transistor is disposed in a second indentation. An upper source/drain region, a channel region, and a lower source/drain region of the transistor are disposed above one another and each adjoin both a first flank of the first indentation and the second indentation. At least a portion of the first flank is provided with a capacitor dielectric, which in the region of the lower source/drain region has a recess, in which the memory node adjoins the lower source/drain region. The second indentation of a first one of the memory cells can adjoin the memory node that is disposed in the first indentation of a second one of the memory cells. The second indentations can be parts of word line trenches, which extend transversely to insulation trenches.

Abstract: A method for producing a microelectronic component of sandwich construction, which includes the steps of providing a first substrate which has a first conductor track plane, providing a plurality of semiconductor chips which have first contact faces electrically connected to the first conductor track plane, and second contact faces opposite the first sides. The method furthermore includes providing a second substrate which has a second conductor track plane with contact points, securing electrically conductive balls to the contact points of the second conductor track plane using an electrically conductive, flexible adhesive, applying an electrically conductive, flexible adhesive to the second contact faces of the plurality of semiconductor chips, and joining the first substrate and the second substrate together.

Abstract: A measuring device has a needle-board circuit board carrying a large number of contact-making needles for contacting connecting areas on an IC circuit. The measuring device has lines for feeding test signals at a high clock frequency to the contact-making needles, and for carrying measured signals away from the contact-making needles. The needles have a shank part with a length L2 and a tip part 14 adjacent thereto with a length L1. For optimally transmitting signals in terms of impedance, the lines are formed as dual-transmission conductor tracks, the shank parts of the contact-making needles each contact a section of the conductor tracks, and the overall length of the contact-making needles satisfies: L1+L2<&lgr;/2, where &lgr; is the maximum wavelength of the signal that is transmitted via a respective line.

Abstract: A trench top isolation (TTI) layer (148) and method of forming thereof for a vertical DRAM. A first assist layer (134) is disposed over trench sidewalls (133) and trench capacitor top surfaces (131). A second assist layer (136) is disposed over the first assist layer (134). The second assist layer (136) is removed from over the trench capacitor top surface (131), and the first assist layer (134) is removed from the trench capacitor top surface (131) using the second assist layer (136) as a mask. The second assist layer (136) is removed, and a first insulating layer (140) is disposed over the first assist layer (134) and trench capacitor top surface (131). A second insulating layer (142) is disposed over the first insulating layer (140), and the second insulating layer (142) is removed from the trench sidewalls (133). The first insulating layer (140) and the first assist layer (134) are removed from the trench sidewalls (133).

Abstract: An active offset cancellation circuit for an open loop differential amplifier is disclosed. The amplifier is operated on a two-phase clock where the normal operation occurs on the first phase and offset detection and cancellation occurs on the second phase. On the second phase, the offset cancellation circuit measures the offset created by the amplifier when both differential inputs are connected to a common source. The circuit then adjusts a bias current and stores this adjustment to cancel offset during the operational phase of the amplifier. During the operational phase, the first phase of the clock, the stored adjustment is used to bias the current in one of the two input stages of the amplifier, canceling any offset imparted by the amplifier circuitry. One each clock cycle, any additional offset is similarly detected and canceled.

Abstract: A synchronous semiconductor memory containing dynamic memory cells has a delay locked loop in order to synchronize a clock signal which actuates data output drivers with an externally supplied clock signal. An updating of the delay locked loop is suppressed during a Read state of the semiconductor memory. An appropriate control signal is produced by a state machine and is supplied to the delay locked loop. The synchronization of the data output with the supplied clock signal can be achieved in a precise manner and requires only simple circuitry.

Abstract: The present invention provides an integrated circuit with a plurality of active strip-shaped regions (S1, D1, S2, D2, S3) arranged in parallel next to one another; a contact level (K2) with a respective plurality of contacts (9′; 11, 12) arranged regularly in the longitudinal direction of the individual strip-shaped regions (S1, D1, S2, D2, S3); the contacts (9′; 11, 12) being arranged in the widthwise direction of the individual strip-shaped regions (S1, D1, S2, D2, S3) in such a way that the widthwise extent of corresponding contacts (9′; 11, 12) of neighboring regions varies.

Abstract: A method for fabricating a trench isolation for electrically active components in a semiconductor component. A mask is applied to a semiconductor substrate. Subsequently, a trench having side walls is formed in the semiconductor substrate by performing a dry etching process using at least one etching gas such that during the dry etching process, polymers are produced that at least partly cover the side walls of the trench and thereby at least partially protect the side walls against an etching attack from the etching gas. The etching gas is provided with a compound that is selected from the group consisting of at least one hydrocarbon compound and a fluorinated hydrocarbon compound. The trench is filled with an insulating oxide.

Abstract: A data carrier, in particular a smart card, is described and has at least one transmitting/receiving antenna and also a rectifier circuit connected downstream thereof and serving for providing a supply voltage for at least one circuit unit. A voltage regulating circuit is connected in parallel with the supply voltage terminals of the circuit unit. The voltage regulating circuit has an output at which a signal proportional to a regulating signal of the voltage regulating circuit can be tapped off. This output is connected to the control input of a controllable clock signal generator, which provides the clock signal for the at least one circuit unit.

Abstract: The device and method compensate for propagation differences between n serial data streams each transmitted over parallel optical lines. Data that can be transmitted via the n serial data streams are configured as m-bit words. The device has n regeneration devices in which data of the data stream can be regenerated. A data output and a clock pulse output of the regeneration devices are connected to a propagation time control device so that the regenerated data and the regenerated clock pulse can be transmitted to a data input or to a clock pulse input of the propagation time control devices. The propagation time control devices each have a demultiplexer for dividing the regenerated data as well as the regenerated clock pulses with a ratio of 1:(x·m), and each have an alignment device for distributing the divided regenerated data on x·m parallel data outputs of the propagation time control devices.

Abstract: A memory cell array has memory cells in which there is an electrical connection between a polycrystalline semiconductor material of a capacitor electrode and a monocrystalline semiconductor region. Islands made of an amorphous material are disposed in a vicinity of the electrical connection between the polycrystalline semiconductor material and the monocrystalline semiconductor region. The islands are produced in particular by thermally breaking up an amorphous layer which has been formed by thermal oxidation. The memory cell array is in particular a DRAM array with a trench capacitor.

Abstract: A multistage power amplifier circuit with superior isolation between gain stages provides alternative common lead currents paths from the individual gain stage elements to obtain improved stability and operational performance.