Abstract: A device includes a thinned semiconductor substrate having a first side and a second side opposite to the first side; and at least one radio frequency device at the first side, wherein the second side of the thinned semiconductor substrate is processed to reduce leakage currents or to improve a radio frequency linearity of the at least one radio frequency device through Bosch etching.

Abstract: A power semiconductor device includes: first and second trenches extending from a surface of a semiconductor body along a vertical direction and laterally confining a mesa region along a first lateral direction; source and body regions in the mesa region electrically connected to a first load terminal; and a first insulation layer having a plurality of insulation blocks, two of which laterally confine a contact hole. The first load terminal extends into the contact hole to contact the source and body regions at the mesa region surface. A first insulation block laterally overlaps with the first trench. A second insulation block laterally overlaps with the second trench. The first insulation block has a first lateral concentration profile of a first implantation material of the source region along the first lateral direction that is different from a corresponding second lateral concentration profile for the second insulation block.

Abstract: A method of manufacturing a lateral transistor is described. The method includes providing a semiconductor substrate. A dielectric layer is formed over the semiconductor substrate. A gate layer is formed over the dielectric layer. A photoresist layer is applied over the gate layer. The photoresist layer is opened by lithography to form a first opening of a first opening size in the photoresist layer. The first opening is transferred into a second opening of a second opening size, the second opening being either formed in the photoresist layer or in an auxiliary layer. A body region is formed in the semiconductor substrate by dopant implantation. Further the gate layer is structured to form a gate edge. An overlap between the structured gate layer and the body region is controlled by an offset between the first opening size and the second opening size.

Abstract: A power semiconductor device includes: a semiconductor body; a control electrode at least partially on or inside the semiconductor body; elevated source regions in the semiconductor body adjacent to the control electrode; recessed body regions adjacent to the elevated source regions; and a dielectric layer arranged on a portion of a surface of the semiconductor body and defining a contact hole. The contact hole is at least partially filled with a conductive material establishing an electrical contact with at least a portion of the elevated source regions and at least a portion of the recessed body regions. At least one first contact surface between at least one elevated source region and the dielectric layer extends in a first horizontal plane. At least one second contact surface between at least one recessed body region and the dielectric layer extends in a second horizontal plane located vertically below the first horizontal plane.

Abstract: A sensor device includes: a semiconductor substrate having a sensing region which extends vertically below a main surface region of the semiconductor substrate into the substrate; a semiconductor capping layer that extends vertically below the main surface region into the substrate; a buried deep trench structure that extends vertically below the capping layer into the substrate and laterally relative to the sensing region, the buried deep trench structure including a doped semiconductor layer that extends from a surface region of the buried deep trench structure into the substrate; a trench doping region that extends from the doped semiconductor layer of the buried deep trench structure into the substrate; and electronic circuitry for the sensing region in a capping region of the substrate vertically above the buried deep trench structure. Methods of manufacturing the sensor device are also provided.

Abstract: A method of manufacturing a semiconductor device includes: forming a trench in a first side of a semiconductor layer, the semiconductor layer including a drift zone of a first conductivity; forming a drain region of the first conductivity type in the first side of the semiconductor layer and laterally adjoining the drift zone; forming a body region of a second conductivity type opposite the first conductivity type and laterally adjoining the drift zone at a side of the drift zone opposite the drain region; and forming source regions of the first conductivity type and body contact regions of the second conductivity type in a sidewall of the trench and arranged in an alternating manner along a length of the trench, using a dopant diffusion process which includes diffusing dopants of both conductivity types from oppositely-doped dopant source layers which are in contact with different regions of the sidewall.

Abstract: A semiconductor device includes a layer stack with first and second semiconductor layers of complementary doping types are arranged alternatingly between first and second surfaces of the layer stack. A first semiconductor region adjoins the first semiconductor layers and has a first end arranged in a first device region and extends from the first end into a second device region. Second semiconductor regions adjoin at least one of the second semiconductor layers. A third semiconductor region adjoins the first semiconductor layers. The first semiconductor region extends from the first device region into the second device region and is spaced apart from the third semiconductor region. The second semiconductor regions are arranged between, and spaced apart from, the third and first semiconductor regions.

Abstract: A semiconductor device includes a layer stack with first semiconductor layers and second semiconductor layers of opposite doping types arranged alternatingly. A first semiconductor region of a first semiconductor device adjoins the first semiconductor layers, and has a first end arranged in a first region of the first semiconductor device and extends from the first end into a second region of the first semiconductor device. Second semiconductor regions of the first semiconductor device adjoin at least one of the second semiconductor layers. A third semiconductor region of the first semiconductor device adjoins the first semiconductor layers. The first semiconductor region extends from the first region into the second region and is spaced apart from the third semiconductor region. The second semiconductor regions are arranged between, and spaced apart from, the third and first semiconductor regions.

Abstract: A power semiconductor switch includes an active cell region with a drift region, an edge termination region, and IGBT cells within the active cell region. Each IGBT cell includes trenches that extend into the drift region and laterally confine mesas. At least one control trench has a control electrode for controlling the load current. At least one dummy trench has a dummy electrode electrically coupled to the control electrode. At least one further trench has a further trench electrode. At least one active mesa is electrically connected to a first load terminal within the active cell region. Each control trench is arranged adjacent to no more than one active mesa. At least one inactive mesa is adjacent to the dummy trench. A cross-trench structure merges each control trench, dummy trench and further trench to each other. The cross-trench structure overlaps at least partially along a vertical direction with the trenches.

Abstract: A power semiconductor switch includes an active cell region with a drift region, an edge termination region, and IGBT cells within the active cell region. Each IGBT cell includes trenches that extend into the drift region and laterally confine mesas. At least one control trench has a control electrode for controlling the load current. At least one dummy trench has a dummy electrode electrically coupled to the control electrode. At least one further trench has a further trench electrode. At least one active mesa is electrically connected to a first load terminal within the active cell region. Each control trench is arranged adjacent to no more than one active mesa. At least one inactive mesa is adjacent to the dummy trench. A cross-trench structure merges each control trench, dummy trench and further trench to each other. The cross-trench structure overlaps at least partially along a vertical direction with the trenches.

Abstract: A method for forming a superjunction transistor device includes: forming a plurality of semiconductor layers one on top of the other; implanting dopant atoms of a first doping type into each semiconductor layer to form first implanted regions in each semiconductor layer; implanting dopant atoms of a second doping type into each semiconductor layer to form second implanted regions in each semiconductor layer. Each of implanting the dopant atoms of the first and second doping types into each semiconductor layer includes forming a respective implantation mask on a respective surface of each semiconductor layer, and at least one of forming the first implanted regions and the second implanted regions in at least one of the semiconductor layers includes a tilted implantation process which uses an implantation vector that is tilted by a tilt angle relative to a normal of the respective horizontal surface of the respective semiconductor layer.

Abstract: A photon avalanche diode includes a semiconductor body having a first side and a second side opposite the first side, a primary doped region of a first conductivity type at the first side of the semiconductor body, a primary doped region of a second conductivity type opposite the first conductivity type at the second side of the semiconductor body, an enhancement region of the second conductivity type below and adjoining the primary doped region of the first conductivity type, the enhancement region forming an active pn-junction with the primary doped region of the first conductivity type, and a collection region of the first conductivity type interposed between the enhancement region and the primary doped region of the second conductivity type and configured to transport a photocarrier generated in the collection region or the primary doped region of the second conductivity type towards the enhancement region.

Abstract: A semiconductor device includes a semiconductor body having a first surface and second surface opposite to the first surface in a vertical direction, and a plurality of transistor cells at least partly integrated in the semiconductor body. Each transistor cell includes at least two source regions, first and second gate electrodes spaced apart from each other in a first horizontal direction and arranged adjacent to and dielectrically insulated from a continuous body region, a drift region separated from the at least two source regions by the body region, and at least three contact plugs extending from the body region towards a source electrode in the vertical direction. The at least three contact plugs are arranged successively between the first and second gate electrodes. Only the two outermost contact plugs that are arranged closest to the first and second gate electrodes, respectively, directly adjoin at least one of the source regions.

Abstract: A method produces a micromechanical sensor element having a first electrode and a second electrode, wherein electrode wall surfaces of the first and the second electrodes are situated opposite one another in a first direction and form a capacitance, wherein one of the first electrode or the second electrode is movable in a second direction, in response to a variable to be detected, and a second one of the first electrode and the second electrode is fixed. The method includes producing a cavity in a semiconductor substrate, the cavity being closed by a doped semiconductor layer; producing the first and the second electrodes in the semiconductor layer, including modifying the electrode wall surface of the first electrode in order to have a smaller extent in the second direction than the electrode wall surface of the second electrode.

Abstract: In an embodiment, a semiconductor die includes a transistor device that has a cell field and an edge termination region, a source pad arranged on the cell field, a gate pad laterally arranged laterally adjacent the cell field and in the edge termination region, a shielding region laterally surrounding the cell field, the shielding region including a non-depletable doped. The polysilicon ESD protection diode is arranged laterally between the gate pad and the source pad and vertically above at least a portion of the shielding region, and includes at least two separate sections that are electrically coupled in parallel between the gate pad and the source pad. The sections are laterally spaced apart by a gap situated at a corner of the gate pad.

Abstract: A semiconductor device includes a semiconductor body comprising a first surface, a second surface opposite to the first surface, an active region, and an edge region surrounding the active region in a horizontal plane. The semiconductor device further includes a plurality of transistor cells at least partly integrated in the active region. Each transistor cell includes a drift region separated from a source region by a body region, and a gate electrode dielectrically insulated from the body region. The semiconductor device also includes a sensor device having a first sensor region of a first doping type integrated in the edge region. The first sensor region is electrically coupled to a first contact pad and to a second contact pad. Each contact pad is arranged either on the first surface or on the second surface. The sensor device at least partially extends around the active region.

Abstract: An electronic circuit is disclosed. The electronic circuit includes: a first transistor device integrated in an inner region of a first semiconductor body; a level shifter integrated in a level shifter region of the first semiconductor body, the level shifter region located in an edge region surrounding the inner region of the semiconductor body; and a drive circuit integrated in a drive circuit region in the edge region of the first semiconductor body, the drive circuit configured to receive a first input signal from a first input and drive the first transistor device based on the first input signal, the drive circuit region arranged closer to the inner region than the level shifter region.

Abstract: A power semiconductor device includes a control cell for controlling a load current. The control cell is electrically connected to a load terminal structure on one side and to a drift region on another side. The drift region includes dopants of a first conductivity type. The control cell includes: a mesa extending along a vertical direction and including: a contact region having dopants of the first conductivity type or of a second conductivity type and electrically connected to the load terminal structure, and a channel region coupled to the drift region; a control electrode configured to induce a conduction channel in the channel region; and a contact plug including a doped semiconductive material and arranged in contact with the contact region. An electrical connection between the contact region and load terminal structure is established by the contact plug, a portion of which projects beyond lateral boundaries of the mesa.

Abstract: A semiconductor device includes a layer stack with a plurality of first semiconductor layers of a first doping type and a plurality of second semiconductor layers of a second doping type complementary to the first doping type. A first semiconductor region of a first semiconductor device adjoins the first semiconductor layers. Each second semiconductor region of the first semiconductor device adjoins at least one of the second semiconductor layers, and is spaced apart from the first semiconductor region. A third semiconductor layer adjoins the layer stack and each first semiconductor region and each second semiconductor region. The third semiconductor layer includes a first region arranged between the first semiconductor region and the second semiconductor region in a first direction. A third semiconductor region of the first or the second doping type extends from a first surface of the third semiconductor layer into the first region.

Abstract: A method of forming a power semiconductor device includes: arranging a control electrode at least partially on or inside a semiconductor body; forming elevated source regions in the semiconductor body by: implanting first conductivity type dopants into the semiconductor body; forming a recess mask layer covering at least areas of intended source regions; and removing portions of the semiconductor body uncovered by the recess mask layer to form the elevated source regions and recessed body regions at least partially between the source regions. A dielectric layer is formed on the semiconductor body. A contact hole mask layer is formed on the dielectric layer. Portions of the dielectric layer uncovered by the contact hole mask layer are removed to form a contact hole which is filled at least partially with a conductive material to establish an electrical contact with at least a portion of the elevated source and recessed body regions.